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Commit fa9fb598 authored by Sahil Chandna's avatar Sahil Chandna Committed by Gerrit - the friendly Code Review server
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power: qpnp-qg: Add support for weighted capacity learning 



Add support to loosen capacity learning qualifying criterion.
This helps to learn capacity from any starting battery SOC to
any ending battery SOC, provided, battery SOC changes by at least
10 % during charging. Assign weight to this capacity learning
event based on the change in battery SOC

Change-Id: I110e0f032c1e402a624abe61e1d9ff06e6c73150
Signed-off-by: default avatarSahil Chandna <chandna@codeaurora.org>
parent ec741aea

Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt

+15 −0
Original line number Diff line number Diff line
@@ -262,6 +262,21 @@ First Level Node - QGAUGE device 
		    capacity learning cycle. If this is not specified, then

		    the default value is 0. Unit is in decipercentage.



- qcom,cl-min-delta-batt-soc

        Usage:      optional

        Value type: <u32>

        Definition: Minimum change in battery SOC to qualify for capacity

                    learning. If this is not specified, then the default

                    value is 10. Unit is in percentage.



- qcom,cl-wt-enable

	Usage:      optional

	Value type: <empty>

	Definition: A boolean property to enable weighted capacity learning

		    based on change in battery SOC during a charging cycle.

		    If this is specified, then "qcom,cl-min-start-soc" and

		    "qcom,cl-max-start-soc" is not used.



- qcom,esr-disable

	Usage:      optional

	Value type: <bool>

drivers/power/supply/qcom/qpnp-qg.c

+9 −0
Original line number Diff line number Diff line
@@ -3296,6 +3296,7 @@ static int qg_alg_init(struct qpnp_qg *chip) 
#define DEFAULT_CL_MAX_DEC_DECIPERC	20

#define DEFAULT_CL_MIN_LIM_DECIPERC	500

#define DEFAULT_CL_MAX_LIM_DECIPERC	100

#define DEFAULT_CL_DELTA_BATT_SOC	10

#define DEFAULT_SHUTDOWN_TEMP_DIFF	60	/* 6 degC */

#define DEFAULT_ESR_QUAL_CURRENT_UA	130000

#define DEFAULT_ESR_QUAL_VBAT_UV	7000
@@ -3594,6 +3595,14 @@ static int qg_parse_dt(struct qpnp_qg *chip) 
		else

			chip->cl->dt.max_cap_limit = temp;



		chip->cl->dt.min_delta_batt_soc = DEFAULT_CL_DELTA_BATT_SOC;

		/* read from DT property and update, if value exists */

		of_property_read_u32(node, "qcom,cl-min-delta-batt-soc",

					&chip->cl->dt.min_delta_batt_soc);



		chip->cl->dt.cl_wt_enable = of_property_read_bool(node,

							"qcom,cl-wt-enable");



		qg_dbg(chip, QG_DEBUG_PON, "DT: cl_min_start_soc=%d cl_max_start_soc=%d cl_min_temp=%d cl_max_temp=%d\n",

			chip->cl->dt.min_start_soc, chip->cl->dt.max_start_soc,

			chip->cl->dt.min_temp, chip->cl->dt.max_temp);