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Commit f873bdd8 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "arm64: ssbd: Add prctl interface for per-thread mitigation"

parents 986b2b1e f022c0ba

Documentation/admin-guide/kernel-parameters.txt

+17 −0
Original line number Diff line number Diff line
@@ -4006,6 +4006,23 @@ 
			expediting.  Set to zero to disable automatic

			expediting.



	ssbd=		[ARM64,HW]

			Speculative Store Bypass Disable control



			On CPUs that are vulnerable to the Speculative

			Store Bypass vulnerability and offer a

			firmware based mitigation, this parameter

			indicates how the mitigation should be used:



			force-on:  Unconditionally enable mitigation for

				   for both kernel and userspace

			force-off: Unconditionally disable mitigation for

				   for both kernel and userspace

			kernel:    Always enable mitigation in the

				   kernel, and offer a prctl interface

				   to allow userspace to register its

				   interest in being mitigated too.



	stack_guard_gap=	[MM]

			override the default stack gap protection. The value

			is in page units and it defines how many pages prior

arch/arm64/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -943,6 +943,14 @@ config PRINT_VMEMLAYOUT 


	  If unsure, say N.



config ARM64_SSBD

	bool "Speculative Store Bypass Disable" if EXPERT

	help

	  This enables mitigation of the bypassing of previous stores

	  by speculative loads.



	  If unsure, say Y.



menuconfig ARMV8_DEPRECATED

	bool "Emulate deprecated/obsolete ARMv8 instructions"

	depends on COMPAT

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -44,7 +44,8 @@ 
#define ARM64_HARDEN_BRANCH_PREDICTOR		24

#define ARM64_HARDEN_BP_POST_GUEST_EXIT		25

#define ARM64_HW_DBM				26

#define ARM64_SSBD				27



#define ARM64_NCAPS				27

#define ARM64_NCAPS				28



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cpufeature.h

+22 −0
Original line number Diff line number Diff line
@@ -23,6 +23,12 @@ 
#define MAX_CPU_FEATURES	(8 * sizeof(elf_hwcap))

#define cpu_feature(x)		ilog2(HWCAP_ ## x)



#define ARM64_SSBD_UNKNOWN		-1

#define ARM64_SSBD_FORCE_DISABLE	0

#define ARM64_SSBD_KERNEL		1

#define ARM64_SSBD_FORCE_ENABLE		2

#define ARM64_SSBD_MITIGATED		3



#ifndef __ASSEMBLY__



#include <linux/bug.h>
@@ -262,6 +268,22 @@ static inline bool system_uses_ttbr0_pan(void) 
		!cpus_have_const_cap(ARM64_HAS_PAN);

}



static inline int arm64_get_ssbd_state(void)

{

#ifdef CONFIG_ARM64_SSBD

	extern int ssbd_state;

	return ssbd_state;

#else

	return ARM64_SSBD_UNKNOWN;

#endif

}



#ifdef CONFIG_ARM64_SSBD

void arm64_set_ssbd_mitigation(bool state);

#else

static inline void arm64_set_ssbd_mitigation(bool state) {}

#endif



#endif /* __ASSEMBLY__ */



#endif

arch/arm64/include/asm/thread_info.h

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ void arch_setup_new_exec(void); 
#define TIF_SINGLESTEP		21

#define TIF_32BIT		22	/* 32bit process */

#define TIF_MM_RELEASED		24

#define TIF_SSBD		25	/* Wants SSB mitigation */



#define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)

#define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)