Merge "Revert "ARM: dts: Update NPU clocks for sm8150"" (986b2b1e) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sm8150-npu.dtsi

+144 −144

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@
		cache-slice-names = "npu";
		cache-slices = <&llcc 23>;
		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,
		<&clock_npucc NPU_CC_CAL_DP_CLK_SRC>,
		<&clock_npucc NPU_CC_XO_CLK>,
		<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,
		<&clock_npucc NPU_CC_BTO_CORE_CLK>,
		@@ -34,15 +35,15 @@
		<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,
		<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,
		<&clock_npucc NPU_CC_NPU_CORE_CLK>,
		<&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>,
		<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,
		<&clock_npucc NPU_CC_NPU_CPC_CLK>,
		<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,
		<&clock_npucc NPU_CC_PERF_CNT_CLK>,
		<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,
		<&clock_npucc NPU_CC_SLEEP_CLK>,
		<&clock_gcc GCC_NPU_AT_CLK>,
		<&clock_gcc GCC_NPU_TRIG_CLK>;
		<&clock_npucc NPU_CC_SLEEP_CLK>;
		clock-names = "cal_dp_clk",
		"cal_dp_clk_src",
		"xo_clk",
		"armwic_core_clk",
		"bto_core_clk",
		@@ -53,14 +54,13 @@
		"npu_core_apb_clk",
		"npu_core_atb_clk",
		"npu_core_clk",
		"npu_core_clk_src",
		"npu_core_cti_clk",
		"npu_cpc_clk",
		"npu_cpc_timer_clk",
		"perf_cnt_clk",
		"qtimer_core_clk",
		"sleep_clk",
		"at_clk",
		"trig_clk";
		"sleep_clk";
		vdd-supply = <&npu_core_gdsc>;
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names ="vdd", "vdd_cx";
		@@ -77,6 +77,7 @@
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		clk-freq = <9600000
		9600000
		19200000
		19200000
		19200000
		@@ -90,15 +91,15 @@
		19200000
		19200000
		19200000
		19200000
		9600000
		19200000
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		clk-freq = <300000000
		300000000
		19200000
		100000000
		19200000
		@@ -109,18 +110,18 @@
		19200000
		60000000
		100000000
		100000000
		37500000
		100000000
		19200000
		300000000
		19200000
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		clk-freq = <350000000
		350000000
		19200000
		150000000
		19200000
		@@ -131,18 +132,18 @@
		19200000
		120000000
		150000000
		150000000
		75000000
		150000000
		19200000
		350000000
		19200000
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		clk-freq = <400000000
		400000000
		19200000
		200000000
		19200000
		@@ -153,18 +154,18 @@
		19200000
		120000000
		200000000
		200000000
		75000000
		200000000
		19200000
		400000000
		19200000
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		clk-freq = <600000000
		600000000
		19200000
		300000000
		19200000
		@@ -175,18 +176,18 @@
		19200000
		240000000
		300000000
		300000000
		150000000
		300000000
		19200000
		600000000
		19200000
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@5 {
		reg = <5>;
		clk-freq = <715000000
		715000000
		19200000
		350000000
		19200000
		@@ -197,13 +198,12 @@
		19200000
		240000000
		350000000
		350000000
		150000000
		350000000
		19200000
		715000000
		19200000
		0
		0
		0>;
		};
		};

drivers/media/platform/msm/npu/npu_dev.c

+8 −6

Original line number	Diff line number	Diff line
		@@ -99,13 +99,13 @@ static void __exit npu_exit(void);
		* -------------------------------------------------------------------------
		*/
		static const char * const npu_clock_order[] = {
		"at_clk",
		"trig_clk",
		"armwic_core_clk",
		"cal_dp_clk_src",
		"cal_dp_clk",
		"cal_dp_cdc_clk",
		"conf_noc_ahb_clk",
		"comp_noc_axi_clk",
		"npu_core_clk_src",
		"npu_core_clk",
		"npu_core_cti_clk",
		"npu_core_apb_clk",
		@@ -126,16 +126,18 @@ static const char * const npu_post_clocks[] = {
		};

		static const char * const npu_exclude_clocks[] = {
		"npu_core_clk_src",
		"cal_dp_clk_src",
		"perf_cnt_clk",
		"npu_core_cti_clk",
		"npu_core_apb_clk",
		"npu_core_atb_clk"
		};

		static const char * const npu_exclude_rate_clocks[] = {
		"at_clk",
		"trig_clk",
		"sleep_clk",
		"xo_clk",
		"conf_noc_ahb_clk",
		"comp_noc_axi_clk",
		"npu_core_cti_clk",
		"npu_core_apb_clk",
		"npu_core_atb_clk",
		@@ -555,7 +557,7 @@ static int npu_enable_core_clocks(struct npu_device *npu_dev, bool post_pil)
		rc = clk_set_rate(core_clks[i].clk,
		pwrlevel->clk_freq[i]);
		if (rc) {
		pr_err("clk_set_rate %s to %ld failed\n",
		pr_debug("clk_set_rate %s to %ld failed\n",
		core_clks[i].clk_name,
		pwrlevel->clk_freq[i]);
		break;