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Commit f71c5adf authored by Alexander Beykun's avatar Alexander Beykun
Browse files

ARM: dts: msm: add 7nm dp phy pll node on SDM855 



Patch sets mdss_dp_pll node as compatible with
"qcom,mdss_dp_pll_7nm" module and adds "gcc_iface"
clock as a dependency on SDM855.

Change-Id: Ia5a949a9a3eaee92f0cfe4e132de31f70becec2c
Signed-off-by: default avatarAlexander Beykun <abeykun@codeaurora.org>
parent 54e85e4c

arch/arm64/boot/dts/qcom/sdm855-sde-pll.dtsi

+5 −4
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -66,7 +66,7 @@ 
	};

	};





	mdss_dp_pll: qcom,mdss_dp_pll@c011000 {

	mdss_dp_pll: qcom,mdss_dp_pll@c011000 {

		compatible = "qcom,mdss_dp_pll_10nm";

		compatible = "qcom,mdss_dp_pll_7nm";

		label = "MDSS DP PLL";

		label = "MDSS DP PLL";

		cell-index = <0>;

		cell-index = <0>;

		#clock-cells = <1>;

		#clock-cells = <1>;
@@ -83,10 +83,11 @@ 




		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "ref_clk",

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"pipe_clk";

			"ref_clk", "pipe_clk";

		clock-rate = <0>;

		clock-rate = <0>;





		qcom,platform-supply-entries {

		qcom,platform-supply-entries {