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Commit 54e85e4c authored by Alexander Beykun's avatar Alexander Beykun
Browse files

clk/qcom/mdss: add 7nm dp phy pll support 



Configure 7nm Display Port PLL. Define and register
DP PLL related clocks to clock framework.

Change-Id: Ieab078392c76ceb0d2626341c0ccba2f1e49e06c
Signed-off-by: default avatarAlexander Beykun <abeykun@codeaurora.org>
parent 6f0f0541

Documentation/devicetree/bindings/fb/mdss-pll.txt

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@@ -17,7 +17,8 @@ Required properties: 
                        "qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8",

                        "qcom,mdss_dsi_pll_10nm", "qcom,mdss_dp_pll_8998",

                        "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm",

                        "qcom,mdss_dsi_pll_7nm".

                        "qcom,mdss_dsi_pll_7nm",

                        "qcom,mdss_dp_pll_7nm".

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

drivers/clk/qcom/mdss/Makefile

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@@ -4,4 +4,5 @@ obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-10nm.o 
obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-10nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-10nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-7nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-7nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-7nm-util.o

drivers/clk/qcom/mdss/mdss-dp-pll-7nm-util.c

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drivers/clk/qcom/mdss/mdss-dp-pll-7nm.c

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drivers/clk/qcom/mdss/mdss-dp-pll-7nm.h

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/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#ifndef __MDSS_DP_PLL_7NM_H

#define __MDSS_DP_PLL_7NM_H



#define DP_VCO_HSCLK_RATE_1620MHZDIV1000	1620000UL

#define DP_VCO_HSCLK_RATE_2700MHZDIV1000	2700000UL

#define DP_VCO_HSCLK_RATE_5400MHZDIV1000	5400000UL

#define DP_VCO_HSCLK_RATE_8100MHZDIV1000	8100000UL



struct dp_pll_db_7nm {

	struct mdss_pll_resources *pll;



	/* lane and orientation settings */

	u8 lane_cnt;

	u8 orientation;



	/* COM PHY settings */

	u32 hsclk_sel;

	u32 dec_start_mode0;

	u32 div_frac_start1_mode0;

	u32 div_frac_start2_mode0;

	u32 div_frac_start3_mode0;

	u32 integloop_gain0_mode0;

	u32 integloop_gain1_mode0;

	u32 vco_tune_map;

	u32 lock_cmp1_mode0;

	u32 lock_cmp2_mode0;

	u32 lock_cmp_en;

	u32 cmn_config;

	u32 txn_tran_drv_emp_en;



	/* PHY vco divider */

	u32 phy_vco_div;

};



int dp_vco_set_rate_7nm(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate);

unsigned long dp_vco_recalc_rate_7nm(struct clk_hw *hw,

				unsigned long parent_rate);

long dp_vco_round_rate_7nm(struct clk_hw *hw, unsigned long rate,

				unsigned long *parent_rate);

int dp_vco_prepare_7nm(struct clk_hw *hw);

void dp_vco_unprepare_7nm(struct clk_hw *hw);

int dp_mux_set_parent_7nm(void *context,

				unsigned int reg, unsigned int val);

int dp_mux_get_parent_7nm(void *context,

				unsigned int reg, unsigned int *val);

#endif /* __MDSS_DP_PLL_7NM_H */