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Commit f7044dd9 authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Ander Conselvan de Oliveira
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drm/i915/glk: Update Port PLL enable sequence for Geminilkae 



Add steps for enabling and disabling Port PLL as per bspec.

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-6-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 51b3ee35

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -1574,6 +1574,8 @@ enum skl_disp_power_wells { 
#define   PORT_PLL_ENABLE		(1 << 31)

#define   PORT_PLL_ENABLE		(1 << 31)

#define   PORT_PLL_LOCK			(1 << 30)

#define   PORT_PLL_LOCK			(1 << 30)

#define   PORT_PLL_REF_SEL		(1 << 27)

#define   PORT_PLL_REF_SEL		(1 << 27)

#define   PORT_PLL_POWER_ENABLE		(1 << 26)

#define   PORT_PLL_POWER_STATE		(1 << 25)

#define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)

#define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)





#define _PORT_PLL_EBB_0_A		0x162034

#define _PORT_PLL_EBB_0_A		0x162034

drivers/gpu/drm/i915/intel_dpll_mgr.c

+20 −0
Original line number Original line Diff line number Diff line
@@ -1380,6 +1380,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 
	temp |= PORT_PLL_REF_SEL;

	temp |= PORT_PLL_REF_SEL;

	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);

	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);





	if (IS_GEMINILAKE(dev_priv)) {

		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));

		temp |= PORT_PLL_POWER_ENABLE;

		I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);



		if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &

				 PORT_PLL_POWER_STATE), 200))

			DRM_ERROR("Power state not set for PLL:%d\n", port);

	}



	/* Disable 10 bit clock */

	/* Disable 10 bit clock */

	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));

	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));

	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;

	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
@@ -1485,6 +1495,16 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 
	temp &= ~PORT_PLL_ENABLE;

	temp &= ~PORT_PLL_ENABLE;

	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);

	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);

	POSTING_READ(BXT_PORT_PLL_ENABLE(port));

	POSTING_READ(BXT_PORT_PLL_ENABLE(port));



	if (IS_GEMINILAKE(dev_priv)) {

		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));

		temp &= ~PORT_PLL_POWER_ENABLE;

		I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);



		if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &

				PORT_PLL_POWER_STATE), 200))

			DRM_ERROR("Power state not reset for PLL:%d\n", port);

	}

}

}





static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,

static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,