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Commit 51b3ee35 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915/glk: Set DCC delay range 2 in PLL enable sequence 



Follow the PLL enable sequence updated in bspec, which requires the DCC
delay range 2 bit to be set.

v2: Moved from DDI init sequence to PLL enable.
v3: Don't read value from GRP register. (Rodrido)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarAnder Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-5-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 0a116ce8

drivers/gpu/drm/i915/i915_reg.h

+15 −0
Original line number Diff line number Diff line
@@ -1784,6 +1784,21 @@ enum skl_disp_power_wells { 
#define   DEEMPH_SHIFT			24

#define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)



#define _PORT_TX_DW5_LN0_A		0x162514

#define _PORT_TX_DW5_LN0_B		0x6C514

#define _PORT_TX_DW5_LN0_C		0x6C914

#define _PORT_TX_DW5_GRP_A		0x162D14

#define _PORT_TX_DW5_GRP_B		0x6CD14

#define _PORT_TX_DW5_GRP_C		0x6CF14

#define BXT_PORT_TX_DW5_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \

							 _PORT_TX_DW5_LN0_B, \

							 _PORT_TX_DW5_LN0_C)

#define BXT_PORT_TX_DW5_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \

							 _PORT_TX_DW5_GRP_B, \

							 _PORT_TX_DW5_GRP_C)

#define   DCC_DELAY_RANGE_1		(1 << 9)

#define   DCC_DELAY_RANGE_2		(1 << 8)



#define _PORT_TX_DW14_LN0_A		0x162538

#define _PORT_TX_DW14_LN0_B		0x6C538

#define _PORT_TX_DW14_LN0_C		0x6C938

drivers/gpu/drm/i915/intel_dpll_mgr.c

+6 −0
Original line number Diff line number Diff line
@@ -1458,6 +1458,12 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 
			200))

		DRM_ERROR("PLL %d not locked\n", port);



	if (IS_GEMINILAKE(dev_priv)) {

		temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));

		temp |= DCC_DELAY_RANGE_2;

		I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);

	}



	/*

	 * While we write to the group register to program all lanes at once we

	 * can read only lane registers and we pick lanes 0/1 for that.