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Commit f331a15f authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/gf100-/gr: unhardcode pagepool config 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent aa2d58c3

drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c

+2 −0
Original line number Diff line number Diff line
@@ -95,4 +95,6 @@ gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_size = 0x3000,

	.bundle_min_gpm_fifo_depth = 0x180,

	.bundle_token_limit = 0x600,

	.pagepool = nve4_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c

+2 −0
Original line number Diff line number Diff line
@@ -54,4 +54,6 @@ gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_size = 0x1800,

	.bundle_min_gpm_fifo_depth = 0x62,

	.bundle_token_limit = 0x100,

	.pagepool = nve4_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c

+18 −8
Original line number Diff line number Diff line
@@ -875,19 +875,26 @@ gm107_grctx_generate_bundle(struct nvc0_grctx *info) 
	mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);

}



static void

gm107_grctx_generate_pagepool(struct nvc0_grctx *info)

{

	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);

	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;

	const int s = 8;

	const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);

	mmio_refn(info, 0x40800c, 0x00000000, s, b);

	mmio_wr32(info, 0x408010, 0x80000000);

	mmio_refn(info, 0x419004, 0x00000000, s, b);

	mmio_wr32(info, 0x419008, 0x00000000);

	mmio_wr32(info, 0x4064cc, 0x80000000);

	mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */

}



static void

gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

{

	mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW);



	mmio_list(0x40800c, 0x00000000,  8, 1);

	mmio_list(0x408010, 0x80000000,  0, 0);

	mmio_list(0x419004, 0x00000000,  8, 1);

	mmio_list(0x419008, 0x00000000,  0, 0);

	mmio_list(0x4064cc, 0x80000000,  0, 0);

	mmio_list(0x418e30, 0x80000000,  0, 0);



	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);

	mmio_list(0x419c2c, 0x10000000, 12, 2);
@@ -944,6 +951,7 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 
	nv_wr32(priv, 0x404154, 0x00000000);



	oclass->bundle(info);

	oclass->pagepool(info);

	oclass->mods(priv, info);

	oclass->unkn(priv);
@@ -1002,4 +1010,6 @@ gm107_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_size = 0x3000,

	.bundle_min_gpm_fifo_depth = 0x180,

	.bundle_token_limit = 0x2c0,

	.pagepool = gm107_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c

+2 −6
Original line number Diff line number Diff line
@@ -538,13 +538,7 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 
	u32 offset;

	int gpc;



	mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);

	mmio_list(0x40800c, 0x00000000,  8, 1);

	mmio_list(0x408010, 0x80000000,  0, 0);

	mmio_list(0x419004, 0x00000000,  8, 1);

	mmio_list(0x419008, 0x00000000,  0, 0);

	mmio_list(0x4064cc, 0x80000000,  0, 0);

	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);
@@ -594,4 +588,6 @@ nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_size = 0x3000,

	.bundle_min_gpm_fifo_depth = 0xc2,

	.bundle_token_limit = 0x200,

	.pagepool = nve4_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c

+16 −5
Original line number Diff line number Diff line
@@ -1033,21 +1033,29 @@ nvc0_grctx_generate_bundle(struct nvc0_grctx *info) 
	mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);

}



void

nvc0_grctx_generate_pagepool(struct nvc0_grctx *info)

{

	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);

	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;

	const int s = 8;

	const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);

	mmio_refn(info, 0x40800c, 0x00000000, s, b);

	mmio_wr32(info, 0x408010, 0x80000000);

	mmio_refn(info, 0x419004, 0x00000000, s, b);

	mmio_wr32(info, 0x419008, 0x00000000);

}



void

nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

{

	int gpc, tpc;

	u32 offset;



	mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);



	mmio_list(0x40800c, 0x00000000,  8, 1);

	mmio_list(0x408010, 0x80000000,  0, 0);

	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);

	mmio_list(0x419004, 0x00000000,  8, 1);

	mmio_list(0x419008, 0x00000000,  0, 0);



	mmio_list(0x405830, 0x02180000, 0, 0);
@@ -1227,6 +1235,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 
	nv_wr32(priv, 0x404154, 0x00000000);



	oclass->bundle(info);

	oclass->pagepool(info);

	oclass->mods(priv, info);

	oclass->unkn(priv);
@@ -1365,4 +1374,6 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.mthd  = nvc0_grctx_pack_mthd,

	.bundle = nvc0_grctx_generate_bundle,

	.bundle_size = 0x1800,

	.pagepool = nvc0_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

}.base;