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Commit aa2d58c3 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/gf100-/gr: unhardcode bundle cb config 



Should be the same values as before, except:

GF117 has smaller buffer allocated, as per register setup.
GK20A now uses values from Tegra driver, not GK104's.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 694c6caf

drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c

+4 −0
Original line number Diff line number Diff line
@@ -91,4 +91,8 @@ gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.ppc   = nvf0_grctx_pack_ppc,

	.icmd  = nvf0_grctx_pack_icmd,

	.mthd  = nvf0_grctx_pack_mthd,

	.bundle = nve4_grctx_generate_bundle,

	.bundle_size = 0x3000,

	.bundle_min_gpm_fifo_depth = 0x180,

	.bundle_token_limit = 0x600,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c

+4 −0
Original line number Diff line number Diff line
@@ -50,4 +50,8 @@ gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.ppc   = nve4_grctx_pack_ppc,

	.icmd  = nve4_grctx_pack_icmd,

	.mthd  = gk20a_grctx_pack_mthd,

	.bundle = nve4_grctx_generate_bundle,

	.bundle_size = 0x1800,

	.bundle_min_gpm_fifo_depth = 0x62,

	.bundle_token_limit = 0x100,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c

+22 −8
Original line number Diff line number Diff line
@@ -858,10 +858,26 @@ gm107_grctx_pack_ppc[] = { 
 * PGRAPH context implementation

 ******************************************************************************/



static void

gm107_grctx_generate_bundle(struct nvc0_grctx *info)

{

	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);

	const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,

				    impl->bundle_size / 0x20);

	const u32 token_limit = impl->bundle_token_limit;

	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;

	const int s = 8;

	const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);

	mmio_refn(info, 0x408004, 0x00000000, s, b);

	mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);

	mmio_refn(info, 0x418e24, 0x00000000, s, b);

	mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b);

	mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);

}



static void

gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

{

	mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW);
@@ -872,13 +888,6 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 
	mmio_list(0x4064cc, 0x80000000,  0, 0);

	mmio_list(0x418e30, 0x80000000,  0, 0);



	mmio_list(0x408004, 0x00000000,  8, 0);

	mmio_list(0x408008, 0x80000030,  0, 0);

	mmio_list(0x418e24, 0x00000000,  8, 0);

	mmio_list(0x418e28, 0x80000030,  0, 0);



	mmio_list(0x4064c8, 0x018002c0,  0, 0);



	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);

	mmio_list(0x419c2c, 0x10000000, 12, 2);
@@ -934,6 +943,7 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 


	nv_wr32(priv, 0x404154, 0x00000000);



	oclass->bundle(info);

	oclass->mods(priv, info);

	oclass->unkn(priv);
@@ -988,4 +998,8 @@ gm107_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.ppc   = gm107_grctx_pack_ppc,

	.icmd  = gm107_grctx_pack_icmd,

	.mthd  = gm107_grctx_pack_mthd,

	.bundle = gm107_grctx_generate_bundle,

	.bundle_size = 0x3000,

	.bundle_min_gpm_fifo_depth = 0x180,

	.bundle_token_limit = 0x2c0,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c

+4 −6
Original line number Diff line number Diff line
@@ -538,7 +538,6 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 
	u32 offset;

	int gpc;



	mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);

	mmio_list(0x40800c, 0x00000000,  8, 1);
@@ -546,11 +545,6 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 
	mmio_list(0x419004, 0x00000000,  8, 1);

	mmio_list(0x419008, 0x00000000,  0, 0);

	mmio_list(0x4064cc, 0x80000000,  0, 0);

	mmio_list(0x408004, 0x00000000,  8, 0);

	mmio_list(0x408008, 0x80000030,  0, 0);

	mmio_list(0x418808, 0x00000000,  8, 0);

	mmio_list(0x41880c, 0x80000030,  0, 0);

	mmio_list(0x4064c8, 0x00c20200,  0, 0);

	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);
@@ -596,4 +590,8 @@ nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.ppc   = nv108_grctx_pack_ppc,

	.icmd  = nv108_grctx_pack_icmd,

	.mthd  = nvf0_grctx_pack_mthd,

	.bundle = nve4_grctx_generate_bundle,

	.bundle_size = 0x3000,

	.bundle_min_gpm_fifo_depth = 0xc2,

	.bundle_token_limit = 0x200,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c

+16 −5
Original line number Diff line number Diff line
@@ -1020,26 +1020,34 @@ nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data, 
	nv_wr32(info->priv, addr, data);

}



void

nvc0_grctx_generate_bundle(struct nvc0_grctx *info)

{

	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);

	const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;

	const int s = 8;

	const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);

	mmio_refn(info, 0x408004, 0x00000000, s, b);

	mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);

	mmio_refn(info, 0x418808, 0x00000000, s, b);

	mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);

}



void

nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

{

	int gpc, tpc;

	u32 offset;



	mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);

	mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);



	mmio_list(0x408004, 0x00000000,  8, 0);

	mmio_list(0x408008, 0x80000018,  0, 0);

	mmio_list(0x40800c, 0x00000000,  8, 1);

	mmio_list(0x408010, 0x80000000,  0, 0);

	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);

	mmio_list(0x419004, 0x00000000,  8, 1);

	mmio_list(0x419008, 0x00000000,  0, 0);

	mmio_list(0x418808, 0x00000000,  8, 0);

	mmio_list(0x41880c, 0x80000018,  0, 0);



	mmio_list(0x405830, 0x02180000, 0, 0);
@@ -1218,6 +1226,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 


	nv_wr32(priv, 0x404154, 0x00000000);



	oclass->bundle(info);

	oclass->mods(priv, info);

	oclass->unkn(priv);
@@ -1354,4 +1363,6 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.tpc   = nvc0_grctx_pack_tpc,

	.icmd  = nvc0_grctx_pack_icmd,

	.mthd  = nvc0_grctx_pack_mthd,

	.bundle = nvc0_grctx_generate_bundle,

	.bundle_size = 0x1800,

}.base;