Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ea5671bf authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

clk: sunxi: Add support for table-based divider clocks 



A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.

This patch adds support for optional divider tables,
so the clock framework will know about the odd values.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 9a5e6c7e

drivers/clk/sunxi/clk-sunxi.c

+5 −4
Original line number Diff line number Diff line
@@ -664,6 +664,7 @@ struct div_data { 
	u8	shift;

	u8	pow;

	u8	width;

	const struct clk_div_table *table;

};



static const struct div_data sun4i_axi_data __initconst = {
@@ -704,10 +705,10 @@ static void __init sunxi_divider_clk_setup(struct device_node *node, 


	of_property_read_string(node, "clock-output-names", &clk_name);



	clk = clk_register_divider(NULL, clk_name, clk_parent, 0,

	clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,

					 reg, data->shift, data->width,

					 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,

				   &clk_lock);

					 data->table, &clk_lock);

	if (clk) {

		of_clk_add_provider(node, of_clk_src_simple_get, clk);

		clk_register_clkdev(clk, clk_name, NULL);