Commit 9a5e6c7e authored Jun 26, 2014 by Chen-Yu Tsai Committed by Maxime Ripard Jul 04, 2014

clk: sunxi: Support factor clocks with N factor starting not from 0



The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.

This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent 70eab199

drivers/clk/sunxi/clk-factors.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -62,7 +62,7 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
		p = FACTOR_GET(config->pshift, config->pwidth, reg);

		/* Calculate the rate */
		rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
		rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);

		return rate;
		}

drivers/clk/sunxi/clk-factors.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -15,6 +15,7 @@ struct clk_factors_config {
		u8 mwidth;
		u8 pshift;
		u8 pwidth;
		u8 n_start;
		};

		struct clk_factors {