Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +3 −6 Original line number Diff line number Diff line Loading @@ -2851,10 +2851,10 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags) } /** * _dsi_ctrl_cache_misr - Cache frame MISR value * dsi_ctrl_cache_misr - Cache frame MISR value * @dsi_ctrl: Pointer to associated dsi_ctrl structure */ static void _dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl) void dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl) { u32 misr; Loading @@ -2869,8 +2869,8 @@ static void _dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl) pr_debug("DSI_%d misr_cache = %x\n", dsi_ctrl->cell_index, dsi_ctrl->misr_cache); } /** * dsi_ctrl_get_host_engine_init_state() - Return host init state * @dsi_ctrl: DSI controller handle. Loading Loading @@ -2968,9 +2968,6 @@ int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl, goto error; } } else if (state == DSI_CTRL_POWER_VREG_OFF) { if (dsi_ctrl->misr_enable) _dsi_ctrl_cache_misr(dsi_ctrl); rc = dsi_ctrl_enable_supplies(dsi_ctrl, false); if (rc) { pr_err("[%d]failed to disable vreg supplies, rc=%d\n", Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +6 −0 Original line number Diff line number Diff line Loading @@ -667,6 +667,12 @@ int dsi_ctrl_setup_misr(struct dsi_ctrl *dsi_ctrl, */ u32 dsi_ctrl_collect_misr(struct dsi_ctrl *dsi_ctrl); /** * dsi_ctrl_cache_misr - Cache frame MISR value * @dsi_ctrl: DSI controller handle. */ void dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl); /** * dsi_ctrl_drv_register() - register platform driver for dsi controller */ Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +11 −1 Original line number Diff line number Diff line Loading @@ -2885,8 +2885,9 @@ int dsi_pre_clkoff_cb(void *priv, enum dsi_clk_type clk, enum dsi_clk_state new_state) { int rc = 0; int rc = 0, i; struct dsi_display *display = priv; struct dsi_display_ctrl *ctrl; if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF)) { /* Loading Loading @@ -2933,6 +2934,15 @@ int dsi_pre_clkoff_cb(void *priv, } /* dsi will not be able to serve irqs from here on */ dsi_display_ctrl_irq_update(display, false); /* cache the MISR values */ for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl) continue; dsi_ctrl_cache_misr(ctrl->ctrl); } } return rc; Loading Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +3 −6 Original line number Diff line number Diff line Loading @@ -2851,10 +2851,10 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags) } /** * _dsi_ctrl_cache_misr - Cache frame MISR value * dsi_ctrl_cache_misr - Cache frame MISR value * @dsi_ctrl: Pointer to associated dsi_ctrl structure */ static void _dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl) void dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl) { u32 misr; Loading @@ -2869,8 +2869,8 @@ static void _dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl) pr_debug("DSI_%d misr_cache = %x\n", dsi_ctrl->cell_index, dsi_ctrl->misr_cache); } /** * dsi_ctrl_get_host_engine_init_state() - Return host init state * @dsi_ctrl: DSI controller handle. Loading Loading @@ -2968,9 +2968,6 @@ int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl, goto error; } } else if (state == DSI_CTRL_POWER_VREG_OFF) { if (dsi_ctrl->misr_enable) _dsi_ctrl_cache_misr(dsi_ctrl); rc = dsi_ctrl_enable_supplies(dsi_ctrl, false); if (rc) { pr_err("[%d]failed to disable vreg supplies, rc=%d\n", Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +6 −0 Original line number Diff line number Diff line Loading @@ -667,6 +667,12 @@ int dsi_ctrl_setup_misr(struct dsi_ctrl *dsi_ctrl, */ u32 dsi_ctrl_collect_misr(struct dsi_ctrl *dsi_ctrl); /** * dsi_ctrl_cache_misr - Cache frame MISR value * @dsi_ctrl: DSI controller handle. */ void dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl); /** * dsi_ctrl_drv_register() - register platform driver for dsi controller */ Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +11 −1 Original line number Diff line number Diff line Loading @@ -2885,8 +2885,9 @@ int dsi_pre_clkoff_cb(void *priv, enum dsi_clk_type clk, enum dsi_clk_state new_state) { int rc = 0; int rc = 0, i; struct dsi_display *display = priv; struct dsi_display_ctrl *ctrl; if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF)) { /* Loading Loading @@ -2933,6 +2934,15 @@ int dsi_pre_clkoff_cb(void *priv, } /* dsi will not be able to serve irqs from here on */ dsi_display_ctrl_irq_update(display, false); /* cache the MISR values */ for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl) continue; dsi_ctrl_cache_misr(ctrl->ctrl); } } return rc; Loading