Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dd17e6b3 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: Remove vdd class voting for xo clock



Remove vdd class from the rcg for video_xo_clk_src to avoid voltage voting
from the branch clock which is marked as always on.

Change-Id: I7a0e452d060c580761e9a8cac2cba4daf00d526b
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 0a887d7e
Loading
Loading
Loading
Loading
+0 −4
Original line number Diff line number Diff line
@@ -158,10 +158,6 @@ static struct clk_rcg2 video_cc_xo_clk_src = {
		.parent_names = video_cc_parent_names_2,
		.num_parents = 2,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
			[VDD_LOWER] = 19200000},
	},
};