Loading arch/arm64/boot/dts/qcom/sm6150.dtsi +61 −0 Original line number Diff line number Diff line Loading @@ -1741,6 +1741,67 @@ status = "disabled"; }; qcom_cedev: qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 272 0>; qcom,bam-pipe-pair = <3>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,bam-ee = <0>; qcom,msm-bus,name = "qcedev-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <125 512 0 0>, <125 512 393600 393600>; qcom,smmu-s1-enable; qcom,no-clock-support; iommus = <&apps_smmu 0x0106 0x0011>, <&apps_smmu 0x0116 0x0011>; }; qcom_crypto: qcrypto@1de0000 { compatible = "qcom,qcrypto"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 272 0>; qcom,bam-pipe-pair = <2>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,bam-ee = <0>; qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; qcom,msm-bus,name = "qcrypto-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <125 512 0 0>, <125 512 393600 393600>; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; qcom,use-sw-ahash-algo; qcom,use-sw-aead-algo; qcom,use-sw-hmac-algo; qcom,smmu-s1-enable; qcom,no-clock-support; iommus = <&apps_smmu 0x0104 0x0011>, <&apps_smmu 0x0114 0x0011>; }; qcom_tzlog: tz-log@146aa720 { compatible = "qcom,tz-log"; reg = <0x146aa720 0x3000>; qcom,hyplog-enabled; hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; }; spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, Loading Loading
arch/arm64/boot/dts/qcom/sm6150.dtsi +61 −0 Original line number Diff line number Diff line Loading @@ -1741,6 +1741,67 @@ status = "disabled"; }; qcom_cedev: qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 272 0>; qcom,bam-pipe-pair = <3>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,bam-ee = <0>; qcom,msm-bus,name = "qcedev-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <125 512 0 0>, <125 512 393600 393600>; qcom,smmu-s1-enable; qcom,no-clock-support; iommus = <&apps_smmu 0x0106 0x0011>, <&apps_smmu 0x0116 0x0011>; }; qcom_crypto: qcrypto@1de0000 { compatible = "qcom,qcrypto"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 272 0>; qcom,bam-pipe-pair = <2>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,bam-ee = <0>; qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; qcom,msm-bus,name = "qcrypto-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <125 512 0 0>, <125 512 393600 393600>; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; qcom,use-sw-ahash-algo; qcom,use-sw-aead-algo; qcom,use-sw-hmac-algo; qcom,smmu-s1-enable; qcom,no-clock-support; iommus = <&apps_smmu 0x0104 0x0011>, <&apps_smmu 0x0114 0x0011>; }; qcom_tzlog: tz-log@146aa720 { compatible = "qcom,tz-log"; reg = <0x146aa720 0x3000>; qcom,hyplog-enabled; hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; }; spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, Loading