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Commit dcc81dc1 authored by Saravana Kannan's avatar Saravana Kannan Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Separate out L3 voting for CPU7 in sm8150 



CPU7 needs a different set of tuning than CPUs 4-6 for L3 scaling. Separate
out the L3 voting for CPU7 to allow this.

Change-Id: Ide1b37de24e8af5b50002be7f799423f7c91af14
Signed-off-by: default avatarSaravana Kannan <skannan@codeaurora.org>
parent 73947aa2

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -921,6 +921,18 @@ 
		< 2841600 1612000000 >;

};



&cpu7_cpu_l3_latmon {

	qcom,core-dev-table =

		<  300000  300000000 >,

		<  825600  614400000 >,

		< 1171200  806400000 >,

		< 1401600  998400000 >,

		< 1708800 1267200000 >,

		< 2016000 1344000000 >,

		< 2419200 1536000000 >,

		< 2841600 1612000000 >;

};



&cpu0_cpu_llcc_latmon {

	qcom,core-dev-table =

		<  300000 MHZ_TO_MBPS( 150, 16) >,

arch/arm64/boot/dts/qcom/sm8150.dtsi

+23 −2
Original line number Diff line number Diff line
@@ -1134,7 +1134,7 @@ 


	cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

		qcom,cpulist = <&CPU4 &CPU5 &CPU6>;

		qcom,target-dev = <&cpu4_cpu_l3_lat>;

		qcom,cachemiss-ev = <0x17>;

		qcom,core-dev-table =
@@ -1146,6 +1146,27 @@ 
			< 2016000 1344000000 >;

	};



	cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_cpucc L3_CLUSTER2_VOTE_CLK>;

		governor = "performance";

	};



	cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU7>;

		qcom,target-dev = <&cpu7_cpu_l3_lat>;

		qcom,cachemiss-ev = <0x17>;

		qcom,core-dev-table =

			<  300000  300000000 >,

			<  768000  576000000 >,

			< 1152000  768000000 >,

			< 1344000  960000000 >,

			< 1689600 1228800000 >,

			< 2016000 1344000000 >;

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";
@@ -1497,7 +1518,7 @@ 
		reg-names = "osm_l3_base", "osm_pwrcl_base",

			"osm_perfcl_base", "osm_perfpcl_base";

		l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat

			&msm_gpu>;

			&msm_gpu &cpu7_cpu_l3_lat>;



		#clock-cells = <1>;

	};