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Commit 73947aa2 authored by David Collins's avatar David Collins
Browse files

clk: qcom: clk-cpu-osm: add cluster 2 voter clock for L3



Add another L3 voter clock associated with cluster 2.  This
will allow cluster 2 to meet its performance requirements.

Change-Id: I8e053618ff56d9d02f51a4ff6f367e3bfb83ff36
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent bead6b39
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+6 −0
Original line number Diff line number Diff line
@@ -305,6 +305,7 @@ static struct clk_osm l3_clk = {

static DEFINE_CLK_VOTER(l3_cluster0_vote_clk, l3_clk, 0);
static DEFINE_CLK_VOTER(l3_cluster1_vote_clk, l3_clk, 0);
static DEFINE_CLK_VOTER(l3_cluster2_vote_clk, l3_clk, 0);
static DEFINE_CLK_VOTER(l3_misc_vote_clk, l3_clk, 0);
static DEFINE_CLK_VOTER(l3_gpu_vote_clk, l3_clk, 0);

@@ -458,6 +459,7 @@ static struct clk_osm cpu7_perfpcl_clk = {
static struct clk_hw *osm_qcom_clk_hws[] = {
	[L3_CLUSTER0_VOTE_CLK] = &l3_cluster0_vote_clk.hw,
	[L3_CLUSTER1_VOTE_CLK] = &l3_cluster1_vote_clk.hw,
	[L3_CLUSTER2_VOTE_CLK] = &l3_cluster2_vote_clk.hw,
	[L3_MISC_VOTE_CLK] = &l3_misc_vote_clk.hw,
	[L3_GPU_VOTE_CLK] = &l3_gpu_vote_clk.hw,
	[L3_CLK] = &l3_clk.hw,
@@ -1037,6 +1039,7 @@ static void clk_cpu_osm_driver_sm6150_fixup(void)
	osm_qcom_clk_hws[CPU5_PERFCL_CLK] = NULL;
	osm_qcom_clk_hws[CPU7_PERFPCL_CLK] = NULL;
	osm_qcom_clk_hws[PERFPCL_CLK] = NULL;
	osm_qcom_clk_hws[L3_CLUSTER2_VOTE_CLK] = NULL;
	osm_qcom_clk_hws[CPU4_PWRCL_CLK] = &cpu4_pwrcl_clk.hw;
	osm_qcom_clk_hws[CPU5_PWRCL_CLK] = &cpu5_pwrcl_clk.hw;
	osm_qcom_clk_hws[CPU7_PERFCL_CLK] = &cpu7_perfcl_clk.hw;
@@ -1053,6 +1056,7 @@ static void clk_cpu_osm_driver_sdmshrike_fixup(void)
{
	osm_qcom_clk_hws[CPU7_PERFPCL_CLK] = NULL;
	osm_qcom_clk_hws[PERFPCL_CLK] = NULL;
	osm_qcom_clk_hws[L3_CLUSTER2_VOTE_CLK] = NULL;
	osm_qcom_clk_hws[CPU7_PERFCL_CLK] = &cpu7_perfcl_clk.hw;

	clk_cpu_map[7] = &cpu7_perfcl_clk;
@@ -1173,6 +1177,8 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev)
			"clk: Failed to enable cluster0 clock for L3\n");
	WARN(clk_prepare_enable(l3_cluster1_vote_clk.hw.clk),
			"clk: Failed to enable cluster1 clock for L3\n");
	WARN(clk_prepare_enable(l3_cluster2_vote_clk.hw.clk),
			"clk: Failed to enable cluster2 clock for L3\n");
	WARN(clk_prepare_enable(l3_misc_vote_clk.hw.clk),
			"clk: Failed to enable misc clock for L3\n");
	WARN(clk_prepare_enable(l3_gpu_vote_clk.hw.clk),
+18 −17
Original line number Diff line number Diff line
@@ -16,22 +16,23 @@

#define L3_CLUSTER0_VOTE_CLK		0
#define L3_CLUSTER1_VOTE_CLK		1
#define L3_MISC_VOTE_CLK		2
#define L3_CLK				3
#define CPU0_PWRCL_CLK			4
#define CPU1_PWRCL_CLK			5
#define CPU2_PWRCL_CLK			6
#define CPU3_PWRCL_CLK			7
#define PWRCL_CLK			8
#define CPU4_PERFCL_CLK			9
#define CPU5_PERFCL_CLK			10
#define CPU6_PERFCL_CLK			11
#define PERFCL_CLK			12
#define CPU7_PERFPCL_CLK		13
#define PERFPCL_CLK			14
#define CPU7_PERFCL_CLK			15
#define L3_GPU_VOTE_CLK			16
#define CPU4_PWRCL_CLK			17
#define CPU5_PWRCL_CLK			18
#define L3_CLUSTER2_VOTE_CLK		2
#define L3_MISC_VOTE_CLK		3
#define L3_GPU_VOTE_CLK			4
#define L3_CLK				5
#define CPU0_PWRCL_CLK			6
#define CPU1_PWRCL_CLK			7
#define CPU2_PWRCL_CLK			8
#define CPU3_PWRCL_CLK			9
#define CPU4_PWRCL_CLK			10
#define CPU5_PWRCL_CLK			11
#define PWRCL_CLK			12
#define CPU4_PERFCL_CLK			13
#define CPU5_PERFCL_CLK			14
#define CPU6_PERFCL_CLK			15
#define CPU7_PERFCL_CLK			16
#define PERFCL_CLK			17
#define CPU7_PERFPCL_CLK		18
#define PERFPCL_CLK			19

#endif