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Commit dc8ec7ba authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I03123e8c,I6a958ebf,I068f5c7d,Ib74cb4ae,I7dd7171d into msm-next 

* changes:
  ARM: dts: msm: add SPMI PMIC arbiter device for sdm855
  defconfig: sdm855: enable regmap debugfs write support
  spmi-pmic-arb: add support to dispatch interrupt based on IRQ status
  spmi: spmi-pmic-arb: check apid against limits before calling irq handler
  spmi: add SPMI PMIC arbiter debug bus driver
parents 072fdbc7 d9a175de

Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb-debug.txt

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+63 −0
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Qualcomm Technologies, Inc. SPMI Debug Controller (PMIC Arbiter)



The SPMI PMIC Arbiter is found on various QTI chips.  It is an SPMI controller

with wrapping arbitration logic to allow for multiple on-chip devices to control

a single SPMI master.



The PMIC Arbiter debug bus is present starting at arbiter version 5.  It has

read and write access to all PMIC peripherals regardless of ownership

configurations.  It cannot be used on production devices because it is disabled

by an eFuse.



See spmi.txt for the generic SPMI controller binding requirements for child

nodes.



Supported Properties:



- compatible

	Usage:      required

	Value type: <string>

	Definition: Must be "qcom,spmi-pmic-arb-debug".



- reg

	Usage:      required

	Value type: <prop-encoded-array>

	Definition: List of address and size pairs.  The address of the PMIC

		    arbiter module is required.  The address of the debug bus

		    disabling fuse is optional.



- reg-names

	Usage:      required

	Value type: <stringlist>

	Definition: Address names. Must include "core" for the PMIC arbiter

		    module and may include "fuse" for the debug bus disabling

		    fuse.  The strings must be specified in the same order as

		    the corresponding addresses are specified in the reg

		    property.



- #address-cells

	Usage:      required

	Value type: <u32>

	Definition: Must be 2.



- #size-cells

	Usage:      required

	Value type: <u32>

	Definition: Must be 0.



- qcom,fuse-disable-bit

	Usage:      required if "fuse" is listed in reg-names property

	Value type: <u32>

	Definition: The bit within the fuse register which is set when the debug

		    bus is not available.  Supported values are 0 to 31.



Example:



qcom,spmi-debug@6b22000 {

	compatible = "qcom,spmi-pmic-arb-debug";

	reg = <0x6b22000 0x60>, <0x7820A8 4>;

	reg-names = "core", "fuse";

	qcom,fuse-disable-bit = <12>;

	#address-cells = <2>;

	#size-cells = <0>;

};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+19 −0
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@@ -679,6 +679,25 @@ 
		#clock-cells = <1>;

	};



	qcom,spmi@c440000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0xc440000 0x1100>,

		      <0xc600000 0x2000000>,

		      <0xe600000 0x100000>,

		      <0xe700000 0xa0000>,

		      <0xc40a000 0x26000>;

		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

		interrupt-names = "periph_irq";

		interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;

		qcom,ee = <0>;

		qcom,channel = <0>;

		#address-cells = <2>;

		#size-cells = <0>;

		interrupt-controller;

		#interrupt-cells = <4>;

		cell-index = <0>;

	};



	pil_modem: qcom,mss@4080000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x4080000 0x100>;

arch/arm64/configs/sdm855-perf_defconfig

+1 −0
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@@ -201,6 +201,7 @@ CONFIG_CFG80211=y 
CONFIG_CFG80211_INTERNAL_REGDB=y

CONFIG_RFKILL=y

CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y

CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y

CONFIG_DMA_CMA=y

CONFIG_ZRAM=y

CONFIG_BLK_DEV_LOOP=y

arch/arm64/configs/sdm855_defconfig

+1 −0
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@@ -209,6 +209,7 @@ CONFIG_CFG80211_INTERNAL_REGDB=y 
# CONFIG_CFG80211_CRDA_SUPPORT is not set

CONFIG_RFKILL=y

CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y

CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y

CONFIG_DMA_CMA=y

CONFIG_ZRAM=y

CONFIG_BLK_DEV_LOOP=y

drivers/spmi/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -24,4 +24,14 @@ config SPMI_MSM_PMIC_ARB 
	  This is required for communicating with Qualcomm PMICs and

	  other devices that have the SPMI interface.



config SPMI_MSM_PMIC_ARB_DEBUG

	tristate "QTI SPMI Debug Controller (PMIC Arbiter)"

	depends on ARCH_QCOM || COMPILE_TEST

	depends on HAS_IOMEM

	help

	  If you say yes to this option, support will be included for the

	  built-in SPMI PMIC Arbiter debug interface on Qualcomm Technologies,

	  Inc. (QTI) MSM family processors.  This feature is available on chips

	  with PMIC arbiter version 5 and above.



endif