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Commit 072fdbc7 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I8f4397e6,I54baa9bc,Ib49bd068 into msm-next 

* changes:
  ARM: dts: msm: Add the clock_debugcc node on SDM855
  defconfig: arm64: Enable the debug CC driver for SDM855
  clk: qcom: gcc-sdm855: Add debug measurement support for shared clocks
parents 236fb315 5f8ac5e4

arch/arm64/boot/dts/qcom/sdm855.dtsi

+17 −5
Original line number Diff line number Diff line
@@ -603,7 +603,7 @@ 
	};



	clock_gcc: qcom,gcc {

		compatible = "qcom,gcc-sdm855";

		compatible = "qcom,gcc-sdm855", "syscon";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;
@@ -613,7 +613,7 @@ 
	};



	clock_videocc: qcom,videocc@ab00000 {

		compatible = "qcom,videocc-sdm855";

		compatible = "qcom,videocc-sdm855", "syscon";

		reg = <0xab00000 0x10000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;
@@ -622,7 +622,7 @@ 
	};



	clock_camcc: qcom,camcc {

		compatible = "qcom,camcc-sdm855";

		compatible = "qcom,camcc-sdm855", "syscon";

		reg = <0xad00000 0x10000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&pm855l_s4_level>;
@@ -631,7 +631,7 @@ 
	};



	clock_dispcc: qcom,dispcc {

		compatible = "qcom,dispcc-sdm855";

		compatible = "qcom,dispcc-sdm855", "syscon";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;
@@ -640,7 +640,7 @@ 
	};



	clock_npucc: qcom,npucc {

		compatible = "qcom,npucc-sdm855";

		compatible = "qcom,npucc-sdm855", "syscon";

		reg = <0x9910000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;
@@ -667,6 +667,18 @@ 
		#clock-cells = <1>;

	};



	clock_debugcc: qcom,cc-debug {

		compatible = "qcom,debugcc-sdm855";

		qcom,gcc = <&clock_gcc>;

		qcom,videocc = <&clock_videocc>;

		qcom,camcc = <&clock_camcc>;

		qcom,dispcc = <&clock_dispcc>;

		qcom,npucc = <&clock_npucc>;

		clock-names = "xo_clk_src";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		#clock-cells = <1>;

	};



	pil_modem: qcom,mss@4080000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x4080000 0x100>;

arch/arm64/configs/sdm855-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -324,6 +324,7 @@ CONFIG_MSM_VIDEOCC_SDM855=y 
CONFIG_MSM_CAMCC_SDM855=y

CONFIG_CLOCK_CPU_OSM=y

CONFIG_MSM_DISPCC_SDM855=y

CONFIG_MSM_DEBUGCC_SDM855=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y

arch/arm64/configs/sdm855_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -334,6 +334,7 @@ CONFIG_MSM_VIDEOCC_SDM855=y 
CONFIG_MSM_CAMCC_SDM855=y

CONFIG_CLOCK_CPU_OSM=y

CONFIG_MSM_DISPCC_SDM855=y

CONFIG_MSM_DEBUGCC_SDM855=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y

drivers/clk/qcom/debugcc-sdm855.c

+12 −0
Original line number Diff line number Diff line
@@ -121,6 +121,10 @@ static const char *const debug_mux_parent_names[] = { 
	"disp_cc_mdss_rscc_vsync_clk",

	"disp_cc_mdss_vsync_clk",

	"disp_cc_xo_clk",

	"measure_only_snoc_clk",

	"measure_only_cnoc_clk",

	"measure_only_bimc_clk",

	"measure_only_ipa_2x_clk",

	"gcc_aggre_noc_pcie_tbu_clk",

	"gcc_aggre_ufs_card_axi_clk",

	"gcc_aggre_ufs_phy_axi_clk",
@@ -472,6 +476,14 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x14, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "disp_cc_xo_clk", 0x56, 1, DISP_CC,

			0x36, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },

		{ "measure_only_snoc_clk", 0x7, 1, GCC,

			0x7, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "measure_only_cnoc_clk", 0x19, 1, GCC,

			0x19, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "measure_only_bimc_clk", 0xD0, 1, GCC,

			0xD0, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "measure_only_ipa_2x_clk", 0x147, 1, GCC,

			0x147, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "gcc_aggre_noc_pcie_tbu_clk", 0x36, 1, GCC,

			0x36, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "gcc_aggre_ufs_card_axi_clk", 0x141, 1, GCC,

drivers/clk/qcom/gcc-sdm855.c

+36 −0
Original line number Diff line number Diff line
@@ -220,6 +220,38 @@ static const char * const gcc_parent_names_9[] = { 
	"core_bi_pll_test_se",

};



static struct clk_dummy measure_only_snoc_clk = {

	.rrate = 1000,

	.hw.init = &(struct clk_init_data){

		.name = "measure_only_snoc_clk",

		.ops = &clk_dummy_ops,

	},

};



static struct clk_dummy measure_only_cnoc_clk = {

	.rrate = 1000,

	.hw.init = &(struct clk_init_data){

		.name = "measure_only_cnoc_clk",

		.ops = &clk_dummy_ops,

	},

};



static struct clk_dummy measure_only_bimc_clk = {

	.rrate = 1000,

	.hw.init = &(struct clk_init_data){

		.name = "measure_only_bimc_clk",

		.ops = &clk_dummy_ops,

	},

};



static struct clk_dummy measure_only_ipa_2x_clk = {

	.rrate = 1000,

	.hw.init = &(struct clk_init_data){

		.name = "measure_only_ipa_2x_clk",

		.ops = &clk_dummy_ops,

	},

};



static struct clk_dummy bi_tcxo = {

	.rrate = 19200000,

	.hw.init = &(struct clk_init_data){
@@ -4120,6 +4152,10 @@ static struct clk_branch gcc_video_xo_clk = { 


struct clk_hw *gcc_sdm855_hws[] = {

	[GCC_XO] = &bi_tcxo.hw,

	[MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw,

	[MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw,

	[MEASURE_ONLY_BIMC_CLK] = &measure_only_bimc_clk.hw,

	[MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw,

};



static struct clk_regmap *gcc_sdm855_clocks[] = {