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Commit 5f8ac5e4 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

ARM: dts: msm: Add the clock_debugcc node on SDM855 



Enable clock measurement support from debugfs.

Change-Id: I8f4397e6f7680bcf76635a8e7b993e451db1511f
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent efe78444

arch/arm64/boot/dts/qcom/sdm855.dtsi

+17 −5
Original line number Original line Diff line number Diff line
@@ -603,7 +603,7 @@ 
	};

	};





	clock_gcc: qcom,gcc {

	clock_gcc: qcom,gcc {

		compatible = "qcom,gcc-sdm855";

		compatible = "qcom,gcc-sdm855", "syscon";

		reg = <0x100000 0x1f0000>;

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx-supply = <&pm855l_s6_level>;
@@ -613,7 +613,7 @@ 
	};

	};





	clock_videocc: qcom,videocc@ab00000 {

	clock_videocc: qcom,videocc@ab00000 {

		compatible = "qcom,videocc-sdm855";

		compatible = "qcom,videocc-sdm855", "syscon";

		reg = <0xab00000 0x10000>;

		reg = <0xab00000 0x10000>;

		reg-names = "cc_base";

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		vdd_mm-supply = <&pm855l_s5_level>;
@@ -622,7 +622,7 @@ 
	};

	};





	clock_camcc: qcom,camcc {

	clock_camcc: qcom,camcc {

		compatible = "qcom,camcc-sdm855";

		compatible = "qcom,camcc-sdm855", "syscon";

		reg = <0xad00000 0x10000>;

		reg = <0xad00000 0x10000>;

		reg-names = "cc_base";

		reg-names = "cc_base";

		vdd_mx-supply = <&pm855l_s4_level>;

		vdd_mx-supply = <&pm855l_s4_level>;
@@ -631,7 +631,7 @@ 
	};

	};





	clock_dispcc: qcom,dispcc {

	clock_dispcc: qcom,dispcc {

		compatible = "qcom,dispcc-sdm855";

		compatible = "qcom,dispcc-sdm855", "syscon";

		reg = <0xaf00000 0x20000>;

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		vdd_mm-supply = <&pm855l_s5_level>;
@@ -640,7 +640,7 @@ 
	};

	};





	clock_npucc: qcom,npucc {

	clock_npucc: qcom,npucc {

		compatible = "qcom,npucc-sdm855";

		compatible = "qcom,npucc-sdm855", "syscon";

		reg = <0x9910000 0x10000>;

		reg = <0x9910000 0x10000>;

		reg-names = "cc_base";

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx-supply = <&pm855l_s6_level>;
@@ -667,6 +667,18 @@ 
		#clock-cells = <1>;

		#clock-cells = <1>;

	};

	};





	clock_debugcc: qcom,cc-debug {

		compatible = "qcom,debugcc-sdm855";

		qcom,gcc = <&clock_gcc>;

		qcom,videocc = <&clock_videocc>;

		qcom,camcc = <&clock_camcc>;

		qcom,dispcc = <&clock_dispcc>;

		qcom,npucc = <&clock_npucc>;

		clock-names = "xo_clk_src";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		#clock-cells = <1>;

	};



	pil_modem: qcom,mss@4080000 {

	pil_modem: qcom,mss@4080000 {

		compatible = "qcom,pil-tz-generic";

		compatible = "qcom,pil-tz-generic";

		reg = <0x4080000 0x100>;

		reg = <0x4080000 0x100>;