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Commit dc60b777 authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
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arm64: mm: use inner-shareable barriers for inner-shareable maintenance 



In order to ensure ordering and completion of inner-shareable maintenance
instructions (cache and TLB) on AArch64, we can use the -ish suffix to
the dmb and dsb instructions respectively.

This patch updates our low-level cache and tlb maintenance routines to
use the inner-shareable barrier variants where appropriate.

Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent ee9e101c

arch/arm64/mm/cache.S

+3 −3
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
 *	Corrupted registers: x0-x7, x9-x11

 */

__flush_dcache_all:

	dsb	sy				// ensure ordering with previous memory accesses

	dmb	sy				// ensure ordering with previous memory accesses

	mrs	x0, clidr_el1			// read clidr

	and	x3, x0, #0x7000000		// extract loc from clidr

	lsr	x3, x3, #23			// left align loc bit field
@@ -128,7 +128,7 @@ USER(9f, dc cvau, x4 ) // clean D line to PoU 
	add	x4, x4, x2

	cmp	x4, x1

	b.lo	1b

	dsb	sy

	dsb	ish



	icache_line_size x2, x3

	sub	x3, x2, #1
@@ -139,7 +139,7 @@ USER(9f, ic ivau, x4 ) // invalidate I line PoU 
	cmp	x4, x1

	b.lo	1b

9:						// ignore any faulting cache operation

	dsb	sy

	dsb	ish

	isb

	ret

ENDPROC(flush_icache_range)

arch/arm64/mm/proc.S

+1 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ ENDPROC(cpu_do_switch_mm) 
ENTRY(__cpu_setup)

	ic	iallu				// I+BTB cache invalidate

	tlbi	vmalle1is			// invalidate I + D TLBs

	dsb	sy

	dsb	ish



	mov	x0, #3 << 20

	msr	cpacr_el1, x0			// Enable FP/ASIMD