Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ee9e101c authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
Browse files

arm64: kvm: use inner-shareable barriers for inner-shareable maintenance 



In order to ensure completion of inner-shareable maintenance instructions
(cache and TLB) on AArch64, we can use the -ish suffix to the dsb
instruction.

This patch relaxes our dsb sy instructions to dsb ish where possible.

Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent d0488597

arch/arm64/kvm/hyp.S

+9 −3
Original line number Diff line number Diff line
@@ -630,9 +630,15 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) 
	 * whole of Stage-1. Weep...

	 */

	tlbi	ipas2e1is, x1

	dsb	sy

	/*

	 * We have to ensure completion of the invalidation at Stage-2,

	 * since a table walk on another CPU could refill a TLB with a

	 * complete (S1 + S2) walk based on the old Stage-2 mapping if

	 * the Stage-1 invalidation happened first.

	 */

	dsb	ish

	tlbi	vmalle1is

	dsb	sy

	dsb	ish

	isb



	msr	vttbr_el2, xzr
@@ -643,7 +649,7 @@ ENTRY(__kvm_flush_vm_context) 
	dsb	ishst

	tlbi	alle1is

	ic	ialluis

	dsb	sy

	dsb	ish

	ret

ENDPROC(__kvm_flush_vm_context)