Merge branch 'for-4.2/ramcode' into for-4.2/emc

       The second entry gives the physical address and length of the

       registers indicating the strapping options.

Optional properties:

- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).

#define APBMISC_SIZE	0x64

#define FUSE_SKU_INFO	0x10

#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT	4

#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG	\

	(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)

#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT	\

	(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)

static void __iomem *apbmisc_base;

static void __iomem *strapping_base;

static bool long_ram_code;

u32 tegra_read_chipid(void)

{

		return 0;

}

u32 tegra_read_ram_code(void)

{

	u32 straps = tegra_read_straps();

	if (long_ram_code)

		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;

	else

		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;

	return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;

}

static const struct of_device_id apbmisc_match[] __initconst = {

	{ .compatible = "nvidia,tegra20-apbmisc", },

	{},

	strapping_base = of_iomap(np, 1);

	if (!strapping_base)

		pr_err("ioremap tegra strapping_base failed\n");

	long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");

}

};

u32 tegra_read_straps(void);

u32 tegra_read_ram_code(void);

u32 tegra_read_chipid(void);

int tegra_fuse_readl(unsigned long offset, u32 *value);