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Commit 6ea2609a authored by Mikko Perttunen's avatar Mikko Perttunen Committed by Thierry Reding
Browse files

soc/tegra: fuse: Add RAM code reader helper 



Needed for the EMC and MC drivers to know what timings from the DT to
use.

Signed-off-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: default avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 405990c7

drivers/soc/tegra/fuse/tegra-apbmisc.c

+21 −0
Original line number Original line Diff line number Diff line
@@ -28,8 +28,15 @@ 
#define APBMISC_SIZE	0x64

#define APBMISC_SIZE	0x64

#define FUSE_SKU_INFO	0x10

#define FUSE_SKU_INFO	0x10





#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT	4

#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG	\

	(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)

#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT	\

	(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)



static void __iomem *apbmisc_base;

static void __iomem *apbmisc_base;

static void __iomem *strapping_base;

static void __iomem *strapping_base;

static bool long_ram_code;





u32 tegra_read_chipid(void)

u32 tegra_read_chipid(void)

{

{
@@ -54,6 +61,18 @@ u32 tegra_read_straps(void) 
		return 0;

		return 0;

}

}





u32 tegra_read_ram_code(void)

{

	u32 straps = tegra_read_straps();



	if (long_ram_code)

		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;

	else

		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;



	return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;

}



static const struct of_device_id apbmisc_match[] __initconst = {

static const struct of_device_id apbmisc_match[] __initconst = {

	{ .compatible = "nvidia,tegra20-apbmisc", },

	{ .compatible = "nvidia,tegra20-apbmisc", },

	{},

	{},
@@ -112,4 +131,6 @@ void __init tegra_init_apbmisc(void) 
	strapping_base = of_iomap(np, 1);

	strapping_base = of_iomap(np, 1);

	if (!strapping_base)

	if (!strapping_base)

		pr_err("ioremap tegra strapping_base failed\n");

		pr_err("ioremap tegra strapping_base failed\n");



	long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");

}
 
}

include/soc/tegra/fuse.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -56,6 +56,7 @@ struct tegra_sku_info { 
};

};





u32 tegra_read_straps(void);

u32 tegra_read_straps(void);

u32 tegra_read_ram_code(void);

u32 tegra_read_chipid(void);

u32 tegra_read_chipid(void);

int tegra_fuse_readl(unsigned long offset, u32 *value);

int tegra_fuse_readl(unsigned long offset, u32 *value);