clk: qcom: Add the display clock driver for SDM855

Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding

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Required properties :

- compatible : Shall contain "qcom,dispcc-sdm855".

- reg : Shall contain base register location and length.

- reg-names: Address name. Must be "cc_base".

- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf

		 of the clocks.

- #clock-cells : Shall contain 1.

- #reset-cells : Shall contain 1.

Example:

	clock_dispcc: qcom,dispcc {

		compatible = "qcom,dispcc-sdm855";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

	 frequency and voltage requests for multiple clusters via the

	 existence of multiple OSM domains.

	 Say Y if you want to support OSM clocks.

config MSM_DISPCC_SDM855

	tristate "SDM855 Display Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the display clock controller on Qualcomm Technologies, Inc

	  SDM855 devices.

	  Say Y if you want to support display devices and functionality such as

	  splash screen.

obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o

obj-$(CONFIG_MSM_CAMCC_SDM855) += camcc-sdm855.o

obj-$(CONFIG_MSM_CLK_AOP_QMP) += clk-aop-qmp.o

obj-$(CONFIG_MSM_DISPCC_SDM855) += dispcc-sdm855.o

obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o

obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o

obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o

#define DISP_CC_MDSS_VSYNC_CLK_SRC				54

#define DISP_CC_PLL0						55

#define DISP_CC_PLL1						56

#define DISP_CC_PLL_TEST_CLK					57

#define DISP_CC_XO_CLK						57

#define DISP_CC_MDSS_CORE_BCR					0

#define DISP_CC_MDSS_RSCC_BCR					1