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Commit 671c45f8 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Update and enable the clock_cpucc node on SDM855 



Update the device tree node for clock_cpucc to move from using
dummy clocks to programming and reading actual OSM base registers.

Change-Id: I9f68536c72fe9e5142d8dfd2e069267d759acd11
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent db74feee

arch/arm64/boot/dts/qcom/sdm855.dtsi

+8 −3
Original line number Diff line number Diff line
@@ -654,10 +654,15 @@ 
	};



	clock_cpucc: qcom,cpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "cpucc_clocks";

		compatible = "qcom,clk-cpu-osm";

		reg = <0x18321000 0x1400>,

			<0x18323000 0x1400>,

			<0x18325800 0x1400>,

			<0x18327800 0x1400>;

		reg-names = "osm_l3_base", "osm_pwrcl_base",

			"osm_perfcl_base", "osm_perfpcl_base";



		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	pil_modem: qcom,mss@4080000 {