Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ced98628 authored by Cyril Chemparathy's avatar Cyril Chemparathy Committed by Kevin Hilman
Browse files

davinci: minor tnetv107x clock tree fixes 



This patch applies the following modifications to the tnetv107x clock tree:

  - reparent tnetv107x usb clocks to usbss

  - mark timer1 as always enabled

  - enable set_rate on pll divider output clocks

  - adjust tnetv107x tsc sysclk rate lower to fix invalid reset defaults

Signed-off-by: default avatarCyril Chemparathy <cyril@ti.com>
Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
parent b1d05be6

arch/arm/mach-davinci/devices-tnetv107x.c

+14 −1
Original line number Diff line number Diff line
@@ -344,7 +344,20 @@ static struct platform_device tsc_device = { 


void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)

{

	int i;

	int i, error;

	struct clk *tsc_clk;



	/*

	 * The reset defaults for tnetv107x tsc clock divider is set too high.

	 * This forces the clock down to a range that allows the ADC to

	 * complete sample conversion in time.

	 */

	tsc_clk = clk_get(NULL, "sys_tsc_clk");

	if (tsc_clk) {

		error = clk_set_rate(tsc_clk, 5000000);

		WARN_ON(error < 0);

		clk_put(tsc_clk);

	}



	platform_device_register(&edma_device);

	platform_device_register(&tnetv107x_wdt_device);

arch/arm/mach-davinci/tnetv107x.c

+12 −11
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ define_pll_clk(eth, 2, 0x0ff, 0x400); 
		.parent		= &pll_##pll##_clk,		\

		.flags		= CLK_PLL,			\

		.div_reg	= PLLDIV##div,			\

		.set_rate	= davinci_set_sysclk_rate,	\

	}



define_pll_div_clk(sys, arm1176,	1);
@@ -192,6 +193,7 @@ lpsc_clk_enabled(system, sys_half_clk, SYSTEM); 
lpsc_clk_enabled(ddr2_vrst,	sys_ddr_clk,	DDR2_EMIF1_VRST);

lpsc_clk_enabled(ddr2_vctl_rst,	sys_ddr_clk,	DDR2_EMIF2_VCTL_RST);

lpsc_clk_enabled(wdt_arm,	sys_half_clk,	WDT_ARM);

lpsc_clk_enabled(timer1,	sys_half_clk,	TIMER1);



lpsc_clk(mbx_lite,	sys_arm1176_clk,	MBX_LITE);

lpsc_clk(ethss,		eth_125mhz_clk,		ETHSS);
@@ -205,16 +207,15 @@ lpsc_clk(mdio, sys_half_clk, MDIO); 
lpsc_clk(sdio0,		sys_half_clk,		SDIO0);

lpsc_clk(sdio1,		sys_half_clk,		SDIO1);

lpsc_clk(timer0,	sys_half_clk,		TIMER0);

lpsc_clk(timer1,	sys_half_clk,		TIMER1);

lpsc_clk(wdt_dsp,	sys_half_clk,		WDT_DSP);

lpsc_clk(ssp,		sys_half_clk,		SSP);

lpsc_clk(tdm0,		tdm_0_clk,		TDM0);

lpsc_clk(tdm1,		tdm_1_clk,		TDM1);

lpsc_clk(vlynq,		sys_vlynq_ref_clk,	VLYNQ);

lpsc_clk(mcdma,		sys_half_clk,		MCDMA);

lpsc_clk(usb0,		sys_half_clk,		USB0);

lpsc_clk(usb1,		sys_half_clk,		USB1);

lpsc_clk(usbss,		sys_half_clk,		USBSS);

lpsc_clk(usb0,		clk_usbss,		USB0);

lpsc_clk(usb1,		clk_usbss,		USB1);

lpsc_clk(ethss_rgmii,	eth_250mhz_clk,		ETHSS_RGMII);

lpsc_clk(imcop,		sys_dsp_clk,		IMCOP);

lpsc_clk(spare,		sys_half_clk,		SPARE);
@@ -281,7 +282,9 @@ static struct clk_lookup clks[] = { 
	CLK(NULL,		"clk_tdm0",		&clk_tdm0),

	CLK(NULL,		"clk_vlynq",		&clk_vlynq),

	CLK(NULL,		"clk_mcdma",		&clk_mcdma),

	CLK(NULL,		"clk_usbss",		&clk_usbss),

	CLK(NULL,		"clk_usb0",		&clk_usb0),

	CLK(NULL,		"clk_usb1",		&clk_usb1),

	CLK(NULL,		"clk_tdm1",		&clk_tdm1),

	CLK(NULL,		"clk_debugss",		&clk_debugss),

	CLK(NULL,		"clk_ethss_rgmii",	&clk_ethss_rgmii),
@@ -289,8 +292,6 @@ static struct clk_lookup clks[] = { 
	CLK(NULL,		"clk_imcop",		&clk_imcop),

	CLK(NULL,		"clk_spare",		&clk_spare),

	CLK("davinci_mmc.1",	NULL,			&clk_sdio1),

	CLK(NULL,		"clk_usb1",		&clk_usb1),

	CLK(NULL,		"clk_usbss",		&clk_usbss),

	CLK(NULL,		"clk_ddr2_vrst",	&clk_ddr2_vrst),

	CLK(NULL,		"clk_ddr2_vctl_rst",	&clk_ddr2_vctl_rst),

	CLK(NULL,		NULL,			NULL),