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Commit cd2fb2e9 authored by Francisco Jerez's avatar Francisco Jerez Committed by Ben Skeggs
Browse files

drm/nv0x-nv4x: Leave the 0x40 bit untouched when changing CRE_LCD. 



It's an unrelated PLL filtering control bit, leave it alone when
changing the CRTC-encoder binding.

Signed-off-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 23357e4d

drivers/gpu/drm/nouveau/nv04_dac.c

+0 −3
Original line number Diff line number Diff line
@@ -345,14 +345,11 @@ static void nv04_dac_prepare(struct drm_encoder *encoder) 
{

	struct drm_encoder_helper_funcs *helper = encoder->helper_private;

	struct drm_device *dev = encoder->dev;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	int head = nouveau_crtc(encoder->crtc)->index;

	struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;



	helper->dpms(encoder, DRM_MODE_DPMS_OFF);



	nv04_dfp_disable(dev, head);

	crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] = 0;

}



static void nv04_dac_mode_set(struct drm_encoder *encoder,

drivers/gpu/drm/nouveau/nv04_dfp.c

+3 −1
Original line number Diff line number Diff line
@@ -104,6 +104,8 @@ void nv04_dfp_disable(struct drm_device *dev, int head) 
	}

	/* don't inadvertently turn it on when state written later */

	crtcstate[head].fp_control = FP_TG_CONTROL_OFF;

	crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=

		~NV_CIO_CRE_LCD_ROUTE_MASK;

}



void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
@@ -253,7 +255,7 @@ static void nv04_dfp_prepare(struct drm_encoder *encoder) 


	nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);



	*cr_lcd = 0x3;

	*cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;



	if (nv_two_heads(dev)) {

		if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)

drivers/gpu/drm/nouveau/nv04_tv.c

+2 −4
Original line number Diff line number Diff line
@@ -99,12 +99,10 @@ static void nv04_tv_bind(struct drm_device *dev, int head, bool bind) 


	state->tv_setup = 0;



	if (bind) {

		state->CRTC[NV_CIO_CRE_LCD__INDEX] = 0;

	if (bind)

		state->CRTC[NV_CIO_CRE_49] |= 0x10;

	} else {

	else

		state->CRTC[NV_CIO_CRE_49] &= ~0x10;

	}



	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX,

		       state->CRTC[NV_CIO_CRE_LCD__INDEX]);

drivers/gpu/drm/nouveau/nv17_tv.c

+1 −3
Original line number Diff line number Diff line
@@ -424,9 +424,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder) 
	}



	if (tv_norm->kind == CTV_ENC_MODE)

		*cr_lcd = 0x1 | (head ? 0x0 : 0x8);

	else

		*cr_lcd = 0;

		*cr_lcd |= 0x1 | (head ? 0x0 : 0x8);



	/* Set the DACCLK register */

	dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;

drivers/gpu/drm/nouveau/nvreg.h

+1 −0
Original line number Diff line number Diff line
@@ -263,6 +263,7 @@ 
#		define NV_CIO_CRE_HCUR_ADDR1_ADR	7:2

#	define NV_CIO_CRE_LCD__INDEX		0x33

#		define NV_CIO_CRE_LCD_LCD_SELECT	0:0

#		define NV_CIO_CRE_LCD_ROUTE_MASK	0x3b

#	define NV_CIO_CRE_DDC0_STATUS__INDEX	0x36

#	define NV_CIO_CRE_DDC0_WR__INDEX	0x37

#	define NV_CIO_CRE_ILACE__INDEX		0x39	/* interlace */