Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 23357e4d authored by Francisco Jerez's avatar Francisco Jerez Committed by Ben Skeggs
Browse files

drm/nv30-nv40: Fix postdivider mask when writing engine/memory PLLs. 



Signed-off-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 2756a4f5

drivers/gpu/drm/nouveau/nouveau_hw.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -305,7 +305,7 @@ setPLL_double_lowregs(struct drm_device *dev, uint32_t NMNMreg, 
	bool mpll = Preg == 0x4020;

	bool mpll = Preg == 0x4020;

	uint32_t oldPval = nvReadMC(dev, Preg);

	uint32_t oldPval = nvReadMC(dev, Preg);

	uint32_t NMNM = pv->NM2 << 16 | pv->NM1;

	uint32_t NMNM = pv->NM2 << 16 | pv->NM1;

	uint32_t Pval = (oldPval & (mpll ? ~(0x11 << 16) : ~(1 << 16))) |

	uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |

			0xc << 28 | pv->log2P << 16;

			0xc << 28 | pv->log2P << 16;

	uint32_t saved4600 = 0;

	uint32_t saved4600 = 0;

	/* some cards have different maskc040s */

	/* some cards have different maskc040s */