MIPS R2 instruction hazard handling. (cc61c1fe) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/mips/mm/c-r4k.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -529,6 +529,7 @@ static void r4k_flush_icache_range(unsigned long __user start,
		args.end = end;

		on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
		instruction_hazard();
		}

		/*

+16 −0

Original line number	Diff line number	Diff line
		@@ -228,6 +228,22 @@ __asm__(

		#endif

		#if defined(CONFIG_CPU_MIPS32_R2) \|\| defined (CONFIG_CPU_MIPS64_R2)
		#define instruction_hazard() \
		do { \
		__label__ __next; \
		__asm__ __volatile__( \
		" jr.hb %0 \n" \
		: \
		: "r" (&&__next)); \
		__next: \
		; \
		} while (0)

		#else
		#define instruction_hazard() do { } while (0)
		#endif

		#endif /* __ASSEMBLY__ */

		#endif /* _ASM_HAZARDS_H */