Loading arch/mips/kernel/cpu-probe.c +5 −0 Original line number Diff line number Diff line Loading @@ -104,6 +104,7 @@ static inline void check_wait(void) /* case CPU_20KC:*/ case CPU_24K: case CPU_25KF: case CPU_34K: cpu_wait = r4k_wait; printk(" available.\n"); break; Loading Loading @@ -538,6 +539,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) /* Probe for L2 cache */ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; break; case PRID_IMP_34K: c->cputype = CPU_34K; c->isa_level = MIPS_CPU_ISA_M32; break; } } Loading arch/mips/kernel/proc.c +1 −0 Original line number Diff line number Diff line Loading @@ -72,6 +72,7 @@ static const char *cpu_name[] = { [CPU_20KC] = "MIPS 20Kc", [CPU_24K] = "MIPS 24K", [CPU_25KF] = "MIPS 25Kf", [CPU_34K] = "MIPS 34K", [CPU_VR4111] = "NEC VR4111", [CPU_VR4121] = "NEC VR4121", [CPU_VR4122] = "NEC VR4122", Loading arch/mips/mm/tlbex.c +1 −0 Original line number Diff line number Diff line Loading @@ -879,6 +879,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_4KEC: case CPU_24K: case CPU_34K: i_ehb(p); tlbw(p); break; Loading include/asm-mips/cpu.h +3 −1 Original line number Diff line number Diff line Loading @@ -77,6 +77,7 @@ #define PRID_IMP_4KEMPR2 0x9100 #define PRID_IMP_4KSD 0x9200 #define PRID_IMP_24K 0x9300 #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_UNKNOWN 0xff00 Loading Loading @@ -185,7 +186,8 @@ #define CPU_AU1550 57 #define CPU_24K 58 #define CPU_AU1200 59 #define CPU_LAST 59 #define CPU_34K 60 #define CPU_LAST 60 /* * ISA Level encodings Loading Loading
arch/mips/kernel/cpu-probe.c +5 −0 Original line number Diff line number Diff line Loading @@ -104,6 +104,7 @@ static inline void check_wait(void) /* case CPU_20KC:*/ case CPU_24K: case CPU_25KF: case CPU_34K: cpu_wait = r4k_wait; printk(" available.\n"); break; Loading Loading @@ -538,6 +539,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) /* Probe for L2 cache */ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; break; case PRID_IMP_34K: c->cputype = CPU_34K; c->isa_level = MIPS_CPU_ISA_M32; break; } } Loading
arch/mips/kernel/proc.c +1 −0 Original line number Diff line number Diff line Loading @@ -72,6 +72,7 @@ static const char *cpu_name[] = { [CPU_20KC] = "MIPS 20Kc", [CPU_24K] = "MIPS 24K", [CPU_25KF] = "MIPS 25Kf", [CPU_34K] = "MIPS 34K", [CPU_VR4111] = "NEC VR4111", [CPU_VR4121] = "NEC VR4121", [CPU_VR4122] = "NEC VR4122", Loading
arch/mips/mm/tlbex.c +1 −0 Original line number Diff line number Diff line Loading @@ -879,6 +879,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_4KEC: case CPU_24K: case CPU_34K: i_ehb(p); tlbw(p); break; Loading
include/asm-mips/cpu.h +3 −1 Original line number Diff line number Diff line Loading @@ -77,6 +77,7 @@ #define PRID_IMP_4KEMPR2 0x9100 #define PRID_IMP_4KSD 0x9200 #define PRID_IMP_24K 0x9300 #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_UNKNOWN 0xff00 Loading Loading @@ -185,7 +186,8 @@ #define CPU_AU1550 57 #define CPU_24K 58 #define CPU_AU1200 59 #define CPU_LAST 59 #define CPU_34K 60 #define CPU_LAST 60 /* * ISA Level encodings Loading