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Commit cc4ee976 authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: qcom: clk-alpha-pll: Use a custom recalc_rate callback for Regera PLL 



The current generic recalc_rate callback that's being used for
Regera PLLs uses the post-divider settings to derive the current
rate for these PLLs. This makes the PLL rate incorrect since the
divider settings are also considered in the corresponding postdiv
operations.
Add a custom recalc_rate callback for the Regera PLLs to fix this
incoherence.

Change-Id: I2cfdd472b3771ab201f5b1d99b8477357474219a
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 8f5dacd1

drivers/clk/qcom/clk-alpha-pll.c

+14 −1
Original line number Diff line number Diff line
@@ -1236,6 +1236,19 @@ static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



static unsigned long

clk_regera_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

	u32 l, frac;

	u64 prate = parent_rate;

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 off = pll->offset;



	regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);

	regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &frac);



	return alpha_pll_calc_rate(pll, prate, l, frac);

}



static void clk_regera_pll_list_registers(struct seq_file *f, struct clk_hw *hw)

{
@@ -1311,7 +1324,7 @@ const struct clk_ops clk_regera_pll_ops = { 
	.enable = clk_regera_pll_enable,

	.disable = clk_regera_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = clk_alpha_pll_recalc_rate,

	.recalc_rate = clk_regera_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_regera_pll_set_rate,

	.list_registers = clk_regera_pll_list_registers,