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Commit 8f5dacd1 authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: qcom: clk-alpha-pll: Do not poll LOCK_DET bit while PLL is disabled 



When a set_rate request comes in for the Regera PLL type today,
on writing to the PLL L_VAL and ALPHA_VAL registers, we check
for the PLL_LOCK_DET bit to be asserted. This is not a valid
check when the PLL is disabled. Return early in that case.

Change-Id: Ib61f5376dc5e6d8b1dd2e415916984cb1f96b88e
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 8aa0accf

drivers/clk/qcom/clk-alpha-pll.c

+8 −1
Original line number Diff line number Diff line
@@ -1199,7 +1199,7 @@ static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long rrate;

	u32 l, off = pll->offset;

	u32 l, regval, off = pll->offset;

	u64 a;

	int ret;
@@ -1217,6 +1217,13 @@ static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, a);

	regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);



	/* Return early if the PLL is disabled */

	ret = regmap_read(pll->clkr.regmap, off + REGERA_PLL_OPMODE, &regval);

	if (ret)

		return ret;

	else if (regval == REGERA_PLL_OFF)

		return 0;



	/* Wait before polling for the frequency latch */

	udelay(5);