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Commit c5689c5f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "Merge commit '681f798f' into dev/msm-4.14-display"

parents c8eb35be 328fc733

Documentation/devicetree/bindings/arm/msm/msm.txt

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@@ -68,6 +68,15 @@ SoCs: 
- TRINKET

  compatible = "qcom,trinket"



- ATOLL

  compatible = "qcom,atoll"



- QCS610

  compatible = "qcom,qcs610"



- QCS410

  compatible = "qcom,qcs410"



Generic board variants:



- CDP device:
@@ -205,3 +214,6 @@ compatible = "qcom,sdmmagpiep-qrd" 
compatible = "qcom,trinket-rumi"

compatible = "qcom,trinket-idp"

compatible = "qcom,trinket-qrd"

compatible = "qcom,atoll-rumi"

compatible = "qcom,qcs610-iot"

compatible = "qcom,qcs410-iot"

Documentation/devicetree/bindings/clock/qcom,virt.txt

+5 −3
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Qualcomm Technologies, Inc. Virtual Clocks



Required properties:

- compatible:	Shall contain:

		"qcom,virt-clk-sm8150".

- compatible:	Shall contain one of the following:

		"qcom,virt-clk-sm8150-gcc",

		"qcom,virt-clk-sm8150-scc".



- #clock-cells:	Shall contain 1.

- #reset-cells:	Shall contain 1.



Example:

	qcom,virtclk {

		compatible = "qcom,virt-clk-sm8150";

		compatible = "qcom,virt-clk-sm8150-gcc";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

Documentation/devicetree/bindings/eeprom/eeprom.txt

+3 −2
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@@ -6,7 +6,8 @@ Required properties: 


	"atmel,24c00", "atmel,24c01", "atmel,24c02", "atmel,24c04",

	"atmel,24c08", "atmel,24c16", "atmel,24c32", "atmel,24c64",

	"atmel,24c128", "atmel,24c256", "atmel,24c512", "atmel,24c1024"

	"atmel,24c128", "atmel,24c256", "atmel,24c512", "atmel,24c1024",

	"atmel,24c2048"



	"catalyst,24c32"
@@ -23,7 +24,7 @@ Required properties: 
	 device with <type> and manufacturer "atmel" should be used.

	 Possible types are:

	 "24c00", "24c01", "24c02", "24c04", "24c08", "24c16", "24c32", "24c64",

	 "24c128", "24c256", "24c512", "24c1024", "spd"

	 "24c128", "24c256", "24c512", "24c1024", "24c2048", "spd"



  - reg : the I2C address of the EEPROM

Documentation/devicetree/bindings/gpu/adreno.txt

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@@ -144,6 +144,14 @@ Optional Properties: 
				mask   - mask for the relevant bits in the efuse register.

				shift  - number of bits to right shift to get the speed bin

				value.



- qcom,gpu-gaming-bin:  	GPU gaming bin information in the format

				<offset mask shift>

				offset - offset of the efuse register from the base.

				mask   - mask for the relevant bits in the efuse register.

				shift  - number of bits to right shift to get the value of

				relevant bits.



- qcom,gpu-disable-fuse:	GPU disable fuse

				<offset mask shift>

				offset - offset of the efuse register from the base.

Documentation/devicetree/bindings/iommu/arm,smmu.txt

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@@ -137,6 +137,15 @@ conditions. 
		  and end of all mapped buffers to prefetch size boundary, which

		  is defined by ARM_SMMU_MIN_IOVA_ALIGN.



- qcom,no-dynamic-asid:

		  Clients that uses the dynamic domains will have an unique asid

		  per each domain and all domains can share the same context bank.

		  When ASID based invalidation is used, on some hardware revisions,

		  as a result of multiple ASID's associated with the same context

		  bank, TLB entries are not invalidated properly. On such systems,

		  we can choose to have a single ASID associated with all domains

		  for a context bank.



- clocks        : List of clocks to be used during SMMU register access. See

                  Documentation/devicetree/bindings/clock/clock-bindings.txt

                  for information about the format. For each clock specified