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Commit c522e063 authored by Tharun Raj Soma's avatar Tharun Raj Soma Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: add split link panel support in dsi driver 



In split link panels, the four data lanes are split into
sublinks and the clock lane is shared among these sublinks.
This change adds support for split link panels in dsi driver.

Change-Id: Idde0d759130aa0a081852f4639224360d3b63142
Signed-off-by: default avatarTharun Raj Soma <tsoma@codeaurora.org>
parent 9b8544be

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+6 −0
Original line number Diff line number Diff line
@@ -371,6 +371,9 @@ Optional properties: 
					resolution restrictions.

- qcom,dcs-cmd-by-left:			Boolean to indicate that dcs command are sent

					through the left DSI controller only in a dual-dsi configuration

- qcom,split-link-enabled:		Boolean to indicate split link support in panel.

- qcom,sublinks-count:			Number of sublinks present in a split link enabled configuration.

- qcom,lanes-per-sublink:		Number of lanes present per sublink in a split link enabled configuration.

- qcom,mdss-dsi-panel-hdr-enabled:      Boolean to indicate HDR support in panel.

- qcom,mdss-dsi-panel-hdr-color-primaries:

                                        Array of 8 unsigned integers denoting chromaticity of panel.These
@@ -642,6 +645,9 @@ Example: 
		qcom,mdss-dsi-lane-1-state;

		qcom,mdss-dsi-lane-2-state;

		qcom,mdss-dsi-lane-3-state;

		qcom,split-link-enabled;

		qcom,sublinks-count = <2>;

		qcom,lanes-per-sublink = <2>;

		qcom,mdss-dsi-t-clk-post = <0x20>;

		qcom,mdss-dsi-t-clk-pre = <0x2c>;

		qcom,mdss-dsi-stream = <0>;

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+7 −0
Original line number Diff line number Diff line
@@ -837,6 +837,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,

	    byte_clk_rate;

	struct dsi_host_common_cfg *host_cfg = &config->common_config;

	struct dsi_split_link_config *split_link = &host_cfg->split_link;

	struct dsi_mode_info *timing = &config->video_timing;



	/* Get bits per pxl in desitnation format */
@@ -851,6 +852,9 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	if (host_cfg->data_lanes & DSI_DATA_LANE_3)

		num_of_lanes++;



	if (split_link->split_link_enabled)

		num_of_lanes = split_link->lanes_per_sublink;



	if (config->bit_clk_rate_hz_override == 0) {

		h_period = DSI_H_TOTAL_DSC(timing);

		v_period = DSI_V_TOTAL(timing);
@@ -1717,6 +1721,9 @@ static int dsi_ctrl_dts_parse(struct dsi_ctrl *dsi_ctrl, 
	dsi_ctrl->null_insertion_enabled = of_property_read_bool(of_node,

					"qcom,null-insertion-enabled");



	dsi_ctrl->split_link_supported = of_property_read_bool(of_node,

					"qcom,split-link-supported");



	return 0;

}

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h

+2 −0
Original line number Diff line number Diff line
@@ -218,6 +218,7 @@ struct dsi_ctrl_interrupts { 
 * @null_insertion_enabled:  A boolean property to allow dsi controller to

 *                           insert null packet.

 * @modeupdated:	  Boolean to send new roi if mode is updated.

 * @split_link_supported: Boolean to check if hw supports split link.

 */

struct dsi_ctrl {

	struct platform_device *pdev;
@@ -271,6 +272,7 @@ struct dsi_ctrl { 
	bool phy_isolation_enabled;

	bool null_insertion_enabled;

	bool modeupdated;

	bool split_link_supported;

};



/**

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c

+35 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
#define DSI_CTRL_DYNAMIC_FORCE_ON         (0x23F|BIT(8)|BIT(9)|BIT(11)|BIT(21))

#define DSI_CTRL_CMD_MISR_ENABLE          BIT(28)

#define DSI_CTRL_VIDEO_MISR_ENABLE        BIT(16)

#define DSI_CTRL_DMA_LINK_SEL             (BIT(12)|BIT(13))

#define DSI_CTRL_MDP0_LINK_SEL            (BIT(20)|BIT(22))



/* Unsupported formats default to RGB888 */

static const u8 cmd_mode_format_map[DSI_PIXEL_FORMAT_MAX] = {
@@ -35,6 +37,38 @@ static const u8 cmd_mode_format_map[DSI_PIXEL_FORMAT_MAX] = { 
static const u8 video_mode_format_map[DSI_PIXEL_FORMAT_MAX] = {

	0x0, 0x1, 0x2, 0x3, 0x3, 0x3, 0x3 };



/**

 * dsi_split_link_setup() - setup dsi split link configurations

 * @ctrl:             Pointer to the controller host hardware.

 * @cfg:              DSI host configuration that is common to both video and

 *                    command modes.

 */

static void dsi_split_link_setup(struct dsi_ctrl_hw *ctrl,

				struct dsi_host_common_cfg *cfg)

{

	u32 reg;



	if (!cfg->split_link.split_link_enabled)

		return;



	reg = DSI_R32(ctrl, DSI_SPLIT_LINK);



	/* DMA_LINK_SEL */

	reg &= ~(0x7 << 12);

	reg |= DSI_CTRL_DMA_LINK_SEL;



	/* MDP0_LINK_SEL */

	reg &= ~(0x7 << 20);

	reg |= DSI_CTRL_MDP0_LINK_SEL;



	/* EN */

	reg |= 0x1;



	/* DSI_SPLIT_LINK */

	DSI_W32(ctrl, DSI_SPLIT_LINK, reg);

	wmb(); /* make sure split link is asserted */

}



/**

 * dsi_setup_trigger_controls() - setup dsi trigger configurations

 * @ctrl:             Pointer to the controller host hardware.
@@ -66,6 +100,7 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl, 
	u32 reg_value = 0;



	dsi_setup_trigger_controls(ctrl, cfg);

	dsi_split_link_setup(ctrl, cfg);



	/* Setup clocking timing controls */

	reg_value = ((cfg->t_clk_post & 0x3F) << 8);

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h

+2 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -191,6 +191,7 @@ 
#define DSI_SECURE_DISPLAY_BLOCK_COMMAND_COLOR     (0x02D0)

#define DSI_SECURE_DISPLAY_BLOCK_VIDEO_COLOR       (0x02D4)

#define DSI_LOGICAL_LANE_SWAP_CTRL                 (0x0310)

#define DSI_SPLIT_LINK                             (0x0330)





#endif /* _DSI_CTRL_REG_H_ */