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Commit bbde4eb5 authored by Dilip Kota's avatar Dilip Kota
Browse files

ARM: dts: msm: Update SPI maximum frequency for QUP instances on QCS405 



BLSP0 QUP2 and BLSP0 QUP3 clock frequencies
are limited to 25Mhz because of timing closure
limitation at hardware level.

Change-Id: Ic45c127df75f8f16607fce5b17692dfe65db1166
Signed-off-by: default avatarDilip Kota <dkota@codeaurora.org>
parent 84932aaa

arch/arm64/boot/dts/qcom/qcs405-blsp.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -220,7 +220,7 @@ 
		      <0x7884000 0x25000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 96 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		spi-max-frequency = <25000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <10>;
@@ -245,7 +245,7 @@ 
		      <0x7884000 0x25000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 97 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		spi-max-frequency = <25000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <12>;