Merge "msm: kgsl: Avoid unnecessary "AHB fence stuck in ISR" error logs" (84932aaa) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/msm/adreno.c

+16 −4

Original line number	Diff line number	Diff line
		@@ -611,6 +611,7 @@ static irqreturn_t adreno_irq_handler(struct kgsl_device *device)
		struct adreno_irq *irq_params = gpudev->irq;
		irqreturn_t ret = IRQ_NONE;
		unsigned int status = 0, fence = 0, fence_retries = 0, tmp, int_bit;
		unsigned int shadow_status = 0;
		int i;

		atomic_inc(&adreno_dev->pending_irq_refcnt);
		@@ -633,18 +634,29 @@ static irqreturn_t adreno_irq_handler(struct kgsl_device *device)
		* and change the fence back to ALLOW. Poll so that this can happen.
		*/
		if (gmu_core_isenabled(device)) {
		do {
		adreno_readreg(adreno_dev,
		ADRENO_REG_GMU_AO_AHB_FENCE_CTRL,
		&fence);

		if (fence_retries == FENCE_RETRY_MAX) {
		while (fence != 0) {
		/* Wait for small time before trying again */
		udelay(1);
		adreno_readreg(adreno_dev,
		ADRENO_REG_GMU_AO_AHB_FENCE_CTRL,
		&fence);

		if (fence_retries == FENCE_RETRY_MAX && fence != 0) {
		adreno_readreg(adreno_dev,
		ADRENO_REG_GMU_RBBM_INT_UNMASKED_STATUS,
		&shadow_status);

		KGSL_DRV_CRIT_RATELIMIT(device,
		"AHB fence stuck in ISR\n");
		"AHB fence stuck in ISR: Shadow INT status=%8.8X\n",
		shadow_status & irq_params->mask);
		goto done;
		}
		fence_retries++;
		} while (fence != 0);
		}
		}

		adreno_readreg(adreno_dev, ADRENO_REG_RBBM_INT_0_STATUS, &status);

+1 −0

Original line number	Diff line number	Diff line
		@@ -723,6 +723,7 @@ enum adreno_regs {
		ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO,
		ADRENO_REG_GMU_NMI_CONTROL_STATUS,
		ADRENO_REG_GMU_CM3_CFG,
		ADRENO_REG_GMU_RBBM_INT_UNMASKED_STATUS,
		ADRENO_REG_GPMU_POWER_COUNTER_ENABLE,
		ADRENO_REG_REGISTER_MAX,
		};

+2 −0

Original line number	Diff line number	Diff line
		@@ -2719,6 +2719,8 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
		A6XX_GMU_NMI_CONTROL_STATUS),
		ADRENO_REG_DEFINE(ADRENO_REG_GMU_CM3_CFG,
		A6XX_GMU_CM3_CFG),
		ADRENO_REG_DEFINE(ADRENO_REG_GMU_RBBM_INT_UNMASKED_STATUS,
		A6XX_GMU_RBBM_INT_UNMASKED_STATUS),
		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,
		A6XX_RBBM_SECVID_TRUST_CNTL),
		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,