Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b99b216b authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata Committed by Ingrid Gallardo
Browse files

ARM: dts: msm: add 7nm DSI pll dtsi entries for sdm shrike 



Add DSI 7nm pll nodes for sdm shrike.

Change-Id: I05004c1d545ba30edd667560c2e394eefb6a8905
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
Signed-off-by: default avatarIngrid Gallardo <ingridg@codeaurora.org>
parent c3afde55

arch/arm64/boot/dts/qcom/sdmshrike-sde-pll.dtsi

0 → 100644
+68 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 {

		compatible = "qcom,mdss_dsi_pll_7nm";

		label = "MDSS DSI 0 PLL";

		cell-index = <0>;

		#clock-cells = <1>;

		reg = <0xae94900 0x260>,

		      <0xae94400 0x800>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "gdsc_base";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 {

		compatible = "qcom,mdss_dsi_pll_7nm";

		label = "MDSS DSI 1 PLL";

		cell-index = <1>;

		#clock-cells = <1>;

		reg = <0xae96900 0x260>,

		      <0xae96400 0x800>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "gdsc_base";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



};

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -334,6 +334,8 @@ 
};



#include "sdmshrike-gdsc.dtsi"

#include "sdmshrike-sde-pll.dtsi"

#include "sdmshrike-sde.dtsi"



&soc {

	#address-cells = <1>;