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Commit c3afde55 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata Committed by Ingrid Gallardo
Browse files

ARM: dts: msm: add displays supported by sdm shrike 



Add various displays for sdmshrike and related panel
configurations to support the same.

Change-Id: If894f5339d402cdb52fbd6f5df0cc0aab6764c14
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
Signed-off-by: default avatarIngrid Gallardo <ingridg@codeaurora.org>
parent 0a606fcd

arch/arm64/boot/dts/qcom/sdmshrike-sde-display.dtsi

0 → 100644
+757 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include "dsi-panel-sim-video.dtsi"

#include "dsi-panel-sim-cmd.dtsi"

#include "dsi-panel-sim-dsc375-cmd.dtsi"

#include "dsi-panel-sim-dualmipi-video.dtsi"

#include "dsi-panel-sim-dualmipi-cmd.dtsi"

#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"

#include "dsi-panel-sharp-dsc-4k-video.dtsi"

#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"

#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"

#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"

#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"

#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"

#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"

#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"

#include "dsi-panel-sharp-1080p-cmd.dtsi"

#include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi"

#include "dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi"

#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"

#include <dt-bindings/clock/mdss-10nm-pll-clk.h>



&soc {

	dsi_panel_pwr_supply: dsi_panel_pwr_supply {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <1800000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};



		qcom,panel-supply-entry@1 {

			reg = <1>;

			qcom,supply-name = "lab";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <100000>;

			qcom,supply-disable-load = <100>;

		};



		qcom,panel-supply-entry@2 {

			reg = <2>;

			qcom,supply-name = "ibb";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <100000>;

			qcom,supply-disable-load = <100>;

			qcom,supply-post-on-sleep = <20>;

		};

	};



	dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <1800000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};

	};



	dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <1800000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};



		qcom,panel-supply-entry@1 {

			reg = <1>;

			qcom,supply-name = "vdd";

			qcom,supply-min-voltage = <3000000>;

			qcom,supply-max-voltage = <3000000>;

			qcom,supply-enable-load = <857000>;

			qcom,supply-disable-load = <0>;

			qcom,supply-post-on-sleep = <0>;

		};

	};



	dsi_sharp_4k_dsc_video_display: qcom,dsi-display@0 {

		compatible = "qcom,dsi-display";

		label = "dsi_sharp_4k_dsc_video_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;



		qcom,dsi-panel = <&dsi_sharp_4k_dsc_video>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_sharp_4k_dsc_cmd_display: qcom,dsi-display@1 {

		compatible = "qcom,dsi-display";

		label = "dsi_sharp_4k_dsc_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;



		qcom,dsi-panel = <&dsi_sharp_4k_dsc_cmd>;

		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_sharp_1080_cmd_display: qcom,dsi-display@2 {

		compatible = "qcom,dsi-display";

		label = "dsi_sharp_1080_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;

		qcom,dsi-panel = <&dsi_sharp_1080_cmd>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_dual_sharp_1080_120hz_cmd_display: qcom,dsi-display@3 {

		compatible = "qcom,dsi-display";

		label = "dsi_dual_sharp_1080_120hz_cmd_display";

		qcom,display-type = "primary";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;

		qcom,dsi-panel = <&dsi_dual_sharp_1080_120hz_cmd>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_dual_nt35597_truly_video_display: qcom,dsi-display@4 {

		compatible = "qcom,dsi-display";

		label = "dsi_dual_nt35597_truly_video_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;

		qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@5 {

		compatible = "qcom,dsi-display";

		label = "dsi_dual_nt35597_truly_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;

		qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@6 {

		compatible = "qcom,dsi-display";

		label = "dsi_nt35597_truly_dsc_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy1>;

		clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			<&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;

		qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@7 {

		compatible = "qcom,dsi-display";

		label = "dsi_nt35597_truly_dsc_video_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy1>;

		clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			<&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;

		qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_sim_vid_display: qcom,dsi-display@8 {

		compatible = "qcom,dsi-display";

		label = "dsi_sim_vid_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;



		qcom,dsi-panel = <&dsi_sim_vid>;

	};



	dsi_dual_sim_vid_display: qcom,dsi-display@9 {

		compatible = "qcom,dsi-display";

		label = "dsi_dual_sim_vid_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;



		qcom,dsi-panel = <&dsi_dual_sim_vid>;

	};



	dsi_sim_cmd_display: qcom,dsi-display@10 {

		compatible = "qcom,dsi-display";

		label = "dsi_sim_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;



		qcom,dsi-panel = <&dsi_sim_cmd>;

	};



	dsi_dual_sim_cmd_display: qcom,dsi-display@11 {

		compatible = "qcom,dsi-display";

		label = "dsi_dual_sim_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;



		qcom,dsi-panel = <&dsi_dual_sim_cmd>;

	};



	dsi_sim_dsc_375_cmd_display: qcom,dsi-display@12 {

		compatible = "qcom,dsi-display";

		label = "dsi_sim_dsc_375_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;



		qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;

	};



	dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@13 {

		compatible = "qcom,dsi-display";

		label = "dsi_dual_sim_dsc_375_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;



		qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;

	};



	dsi_sw43404_amoled_cmd_display: qcom,dsi-display@14 {

		compatible = "qcom,dsi-display";

		label = "dsi_sw43404_amoled_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;



		qcom,dsi-panel = <&dsi_sw43404_amoled_cmd>;

		vddio-supply = <&pm855p_l1>;

	};



	dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@15 {

		compatible = "qcom,dsi-display";

		label = "dsi_nt35695b_truly_fhd_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;



		qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@16 {

		compatible = "qcom,dsi-display";

		label = "dsi_nt35695b_truly_fhd_video_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;

		qcom,platform-te-gpio = <&tlmm 8 0>;

		qcom,platform-reset-gpio = <&tlmm 7 0>;

		qcom,panel-mode-gpio = <&tlmm 6 0>;



		qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>;



		vddio-supply = <&pm855p_l1>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;

	};



	sde_wb: qcom,wb-display@0 {

		compatible = "qcom,wb-display";

		cell-index = <0>;

		label = "wb_display";

	};



	ext_disp: qcom,msm-ext-disp {

		compatible = "qcom,msm-ext-disp";



		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {

			compatible = "qcom,msm-ext-disp-audio-codec-rx";

		};

	};

};



&mdss_mdp {

	connectors = <&sde_wb>;

};



/* PHY TIMINGS REVISION P */

&dsi_dual_nt35597_truly_video {

	qcom,mdss-dsi-t-clk-post = <0x17>;

	qcom,mdss-dsi-t-clk-pre = <0x18>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07

				07 05 03 04 00 18 17];

			qcom,display-topology = <2 0 2>,

						<1 0 2>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_dual_nt35597_truly_cmd {

	qcom,mdss-dsi-t-clk-post = <0x17>;

	qcom,mdss-dsi-t-clk-pre = <0x18>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07

				07 05 03 04 00 18 17];

			qcom,display-topology = <2 0 2>,

						<1 0 2>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_nt35597_truly_dsc_cmd {

	qcom,mdss-dsi-t-clk-post = <0x15>;

	qcom,mdss-dsi-t-clk-pre = <0x12>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05

				05 03 03 04 00 12 15];

			qcom,display-topology = <1 1 1>,

						<2 2 1>, /* dsc merge */

						<2 1 1>; /* 3d mux */

			qcom,default-topology-index = <1>;

		};

	};

};



&dsi_nt35597_truly_dsc_video {

	qcom,mdss-dsi-t-clk-post = <0x15>;

	qcom,mdss-dsi-t-clk-pre = <0x12>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05

				05 03 03 04 00 12 15];

			qcom,display-topology = <1 1 1>,

						<2 2 1>, /* dsc merge */

						<2 1 1>; /* 3d mux */

			qcom,default-topology-index = <1>;

		};

	};

};



&dsi_sharp_4k_dsc_video {

	qcom,mdss-dsi-t-clk-post = <0x18>;

	qcom,mdss-dsi-t-clk-pre = <0x19>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08

				08 05 03 04 00 19 18];

			qcom,display-topology = <2 2 2>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sharp_4k_dsc_cmd {

	qcom,mdss-dsi-t-clk-post = <0x18>;

	qcom,mdss-dsi-t-clk-pre = <0x19>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08

				08 05 03 04 00 19 18];

			qcom,display-topology = <2 2 2>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_nt35695b_truly_fhd_video {

	qcom,mdss-dsi-t-clk-post = <0x17>;

	qcom,mdss-dsi-t-clk-pre = <0x19>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22

				08 08 05 03 04 00 19 17];

			qcom,display-topology = <1 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_nt35695b_truly_fhd_cmd {

	qcom,mdss-dsi-t-clk-post = <0x17>;

	qcom,mdss-dsi-t-clk-pre = <0x19>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22

				08 08 05 03 04 00 19 17];

			qcom,display-topology = <1 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_dual_sharp_1080_120hz_cmd {

	qcom,mdss-dsi-t-clk-post = <0x0f>;

	qcom,mdss-dsi-t-clk-pre = <0x36>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09

				09 06 03 04 00];

			qcom,display-topology = <2 0 2>,

						<1 0 2>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sharp_1080_cmd {

	qcom,mdss-dsi-t-clk-post = <0x0c>;

	qcom,mdss-dsi-t-clk-pre = <0x29>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07

				07 04 03 04 00];

			qcom,display-topology = <1 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sim_vid {

	qcom,mdss-dsi-t-clk-post = <0x0d>;

	qcom,mdss-dsi-t-clk-pre = <0x2d>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [01 03 01 00 01 01 01

				01 00 03 04 00 03 04];

			qcom,display-topology = <1 0 1>,

						<2 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_dual_sim_vid {

	qcom,mdss-dsi-t-clk-post = <0x0d>;

	qcom,mdss-dsi-t-clk-pre = <0x2d>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03

				03 02 03 04 00 10 06];

			qcom,display-topology = <2 0 2>,

						<1 0 2>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sim_cmd {

	qcom,mdss-dsi-t-clk-post = <0x0d>;

	qcom,mdss-dsi-t-clk-pre = <0x2d>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 03 01 00 01 01 02

				01 00 03 04 00 03 04];

			qcom,display-topology = <1 0 1>,

						<2 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_dual_sim_cmd {

	qcom,mdss-dsi-t-clk-post = <0x0d>;

	qcom,mdss-dsi-t-clk-pre = <0x2d>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03

				03 02 03 04 00 10 06];

			qcom,display-topology = <2 0 2>;

			qcom,default-topology-index = <0>;

		};

		timing@1{

			qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03

				03 02 03 04 00 10 06];

			qcom,display-topology = <2 0 2>,

						<1 0 2>;

			qcom,default-topology-index = <0>;

		};

		timing@2{

			qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03

				03 02 03 04 00 10 06];

			qcom,display-topology = <2 0 2>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sim_dsc_375_cmd {

	qcom,mdss-dsi-t-clk-post = <0x0d>;

	qcom,mdss-dsi-t-clk-pre = <0x2d>;

	qcom,mdss-dsi-display-timings {

		timing@0 { /* 1080p */

			qcom,mdss-dsi-panel-phy-timings = [00 12 03 04 07 07 04

				04 03 03 04 00 13 07];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};

		timing@1 { /* qhd */

			qcom,mdss-dsi-panel-phy-timings = [00 12 03 04 07 07 04

				04 03 03 04 00 13 07];

			qcom,display-topology = <1 1 1>,

						<2 2 1>, /* dsc merge */

						<2 1 1>; /* 3d mux */

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_dual_sim_dsc_375_cmd {

	qcom,mdss-dsi-t-clk-post = <0x0d>;

	qcom,mdss-dsi-t-clk-pre = <0x2d>;

	qcom,mdss-dsi-display-timings {

		timing@0 { /* qhd */

			qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03

				03 02 03 04 00 10 06];

			qcom,display-topology = <2 2 2>;

			qcom,default-topology-index = <0>;

		};

		timing@1 { /* 4k */

			qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03

				03 02 03 04 00 10 06];

			qcom,display-topology = <2 2 2>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sw43404_amoled_cmd {

	qcom,mdss-dsi-t-clk-post = <0x16>;

	qcom,mdss-dsi-t-clk-pre = <0x16>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07

				07 04 03 04 00 16 16];

			qcom,display-topology = <2 2 1>;

			qcom,default-topology-index = <0>;

		};

	};

};