Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b84ef567 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata
Browse files

drm/msm/dsi-staging: reset clk enable select bit after FIFO resync 



For each clock state change on DSI link clocks, toggling
of resync fifo register is needed. During this operation
clk_en_sel bit should be set high per latest hardware
specification. After resync fifo is toggled, clk_en_sel
bit has to be unset.

Change-Id: Ie2bac6a12aac7d0f81a819d5d20964b521ec0307
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent d435978d

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -244,6 +244,7 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy) 
	phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v4_0;

	phy->ops.phy_lane_reset = dsi_phy_hw_v4_0_lane_reset;

	phy->ops.toggle_resync_fifo = dsi_phy_hw_v4_0_toggle_resync_fifo;

	phy->ops.reset_clk_en_sel = dsi_phy_hw_v4_0_reset_clk_en_sel;

}



/**

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+1 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ int dsi_phy_hw_timing_val_v4_0(struct dsi_phy_per_lane_cfgs *timing_cfg, 
		u32 *timing_val, u32 size);

int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy);

void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy);

void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy);



/* DSI controller common ops */

u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+10 −0
Original line number Diff line number Diff line
@@ -1904,6 +1904,16 @@ static void dsi_display_toggle_resync_fifo(struct dsi_display *display) 
		ctrl = &display->ctrl[i];

		dsi_phy_toggle_resync_fifo(ctrl->phy);

	}



	/*

	 * After retime buffer synchronization we need to turn of clk_en_sel

	 * bit on each phy.

	 */

	for (i = 0; i < display->ctrl_count; i++) {

		ctrl = &display->ctrl[i];

		dsi_phy_reset_clk_en_sel(ctrl->phy);

	}



}



static int dsi_display_ctrl_update(struct dsi_display *display)

drivers/gpu/drm/msm/dsi-staging/dsi_phy.c

+12 −0
Original line number Diff line number Diff line
@@ -775,6 +775,18 @@ void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy) 
	phy->hw.ops.toggle_resync_fifo(&phy->hw);

}





void dsi_phy_reset_clk_en_sel(struct msm_dsi_phy *phy)

{

	if (!phy)

		return;



	if (!phy->hw.ops.reset_clk_en_sel)

		return;



	phy->hw.ops.reset_clk_en_sel(&phy->hw);

}



int dsi_phy_set_ulps(struct msm_dsi_phy *phy, struct dsi_host_config *config,

		bool enable, bool clamp_enabled)

{

drivers/gpu/drm/msm/dsi-staging/dsi_phy.h

+9 −0
Original line number Diff line number Diff line
@@ -259,6 +259,15 @@ int dsi_phy_lane_reset(struct msm_dsi_phy *phy); 
 */

void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy);



/**

 * dsi_phy_reset_clk_en_sel() - reset clk_en_select on cmn_clk_cfg1 register

 * @phy:          DSI PHY handle

 *

 * After toggling resync fifo regiater, clk_en_sel bit on cmn_clk_cfg1

 * register has to be reset

 */

void dsi_phy_reset_clk_en_sel(struct msm_dsi_phy *phy);



/**

 * dsi_phy_drv_register() - register platform driver for dsi phy

 */