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Commit d435978d authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata
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drivers: clk: qcom: enable clk enable select bit during FIFO resync 



For each clock state change on DSI link clocks, toggling
of resync fifo register is needed. During this operation
clk_en_sel bit should be set high per hardware
recommendations.

Change-Id: Ie1ee73d36d5add929a72796c465d3850c1d61f2a
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent a04d5c07

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+4 −1
Original line number Diff line number Diff line
@@ -896,7 +896,10 @@ static void dsi_pll_enable_global_clk(struct mdss_pll_resources *rsc) 
	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_3, 0x04);



	data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1);

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data | BIT(5)));



	/* Turn on clk_en_sel bit prior to resync toggle fifo */

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data | BIT(5) |

								BIT(4)));

}



static void dsi_pll_phy_dig_reset(struct mdss_pll_resources *rsc)