Loading arch/arm64/boot/dts/qcom/sm8150-smp2p.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -32,6 +32,18 @@ interrupt-controller; #interrupt-cells = <2>; }; smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; /* ipa - inbound entry from mss */ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-adsp@1799000c { Loading arch/arm64/boot/dts/qcom/sm8150.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -3278,6 +3278,19 @@ "TURBO"; qcom,throughput-threshold = <310 600 1000>; qcom,scaling-exceptions = <>; /* smp2p information */ qcom,smp2p_map_ipa_1_out { compatible = "qcom,smp2p-map-ipa-1-out"; qcom,smem-states = <&smp2p_ipa_1_out 0>; qcom,smem-state-names = "ipa-smp2p-out"; }; qcom,smp2p_map_ipa_1_in { compatible = "qcom,smp2p-map-ipa-1-in"; interrupts-extended = <&smp2p_ipa_1_in 0 0>; interrupt-names = "ipa-smp2p-in"; }; }; ipa_smmu_ap: ipa_smmu_ap { Loading Loading
arch/arm64/boot/dts/qcom/sm8150-smp2p.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -32,6 +32,18 @@ interrupt-controller; #interrupt-cells = <2>; }; smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; /* ipa - inbound entry from mss */ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-adsp@1799000c { Loading
arch/arm64/boot/dts/qcom/sm8150.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -3278,6 +3278,19 @@ "TURBO"; qcom,throughput-threshold = <310 600 1000>; qcom,scaling-exceptions = <>; /* smp2p information */ qcom,smp2p_map_ipa_1_out { compatible = "qcom,smp2p-map-ipa-1-out"; qcom,smem-states = <&smp2p_ipa_1_out 0>; qcom,smem-state-names = "ipa-smp2p-out"; }; qcom,smp2p_map_ipa_1_in { compatible = "qcom,smp2p-map-ipa-1-in"; interrupts-extended = <&smp2p_ipa_1_in 0 0>; interrupt-names = "ipa-smp2p-in"; }; }; ipa_smmu_ap: ipa_smmu_ap { Loading