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Commit b7630473 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: rework GPU reset on evergreen 



Update the code to better match the recommended
programming sequence for soft reset.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d3cb781e

drivers/gpu/drm/radeon/evergreen.c

+85 −76
Original line number Diff line number Diff line
@@ -2327,54 +2327,8 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin 
	return radeon_ring_test_lockup(rdev, ring);

}



static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)

static void evergreen_print_gpu_status_regs(struct radeon_device *rdev)

{

	u32 grbm_reset = 0;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		return;



	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",

		RREG32(GRBM_STATUS_SE0));

	dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",

		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",

		RREG32(SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));



	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);



	/* reset all the gfx blocks */

	grbm_reset = (SOFT_RESET_CP |

		      SOFT_RESET_CB |

		      SOFT_RESET_DB |

		      SOFT_RESET_PA |

		      SOFT_RESET_SC |

		      SOFT_RESET_SPI |

		      SOFT_RESET_SH |

		      SOFT_RESET_SX |

		      SOFT_RESET_TC |

		      SOFT_RESET_TA |

		      SOFT_RESET_VC |

		      SOFT_RESET_VGT);



	dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);

	WREG32(GRBM_SOFT_RESET, grbm_reset);

	(void)RREG32(GRBM_SOFT_RESET);

	udelay(50);

	WREG32(GRBM_SOFT_RESET, 0);

	(void)RREG32(GRBM_SOFT_RESET);



	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
@@ -2391,29 +2345,6 @@ static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev) 
		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

}



static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)

{

	u32 tmp;



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		return;



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));



	/* Disable DMA */

	tmp = RREG32(DMA_RB_CNTL);

	tmp &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL, tmp);



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));

}
@@ -2421,9 +2352,12 @@ static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev) 
static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

	struct evergreen_mc_save save;

	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

	u32 tmp;

	int ret = 0;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);

		reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP);



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		reset_mask &= ~RADEON_RESET_DMA;
@@ -2433,6 +2367,8 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 


	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);



	evergreen_print_gpu_status_regs(rdev);



	r600_set_bios_scratch_engine_hung(rdev, true);



	evergreen_mc_stop(rdev, &save);
@@ -2440,19 +2376,91 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))

		evergreen_gpu_soft_reset_gfx(rdev);

	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);



	if (reset_mask & RADEON_RESET_DMA) {

		/* Disable DMA */

		tmp = RREG32(DMA_RB_CNTL);

		tmp &= ~DMA_RB_ENABLE;

		WREG32(DMA_RB_CNTL, tmp);

	}



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {

		grbm_soft_reset |= SOFT_RESET_DB |

			SOFT_RESET_CB |

			SOFT_RESET_PA |

			SOFT_RESET_SC |

			SOFT_RESET_SPI |

			SOFT_RESET_SX |

			SOFT_RESET_SH |

			SOFT_RESET_TC |

			SOFT_RESET_TA |

			SOFT_RESET_VC |

			SOFT_RESET_VGT;

	}



	if (reset_mask & RADEON_RESET_CP) {

		grbm_soft_reset |= SOFT_RESET_CP |

			SOFT_RESET_VGT;



		srbm_soft_reset |= SOFT_RESET_GRBM;

	}



	if (reset_mask & RADEON_RESET_DMA)

		evergreen_gpu_soft_reset_dma(rdev);

		srbm_soft_reset |= SOFT_RESET_DMA;



	if (grbm_soft_reset) {

		tmp = RREG32(GRBM_SOFT_RESET);

		tmp |= grbm_soft_reset;

		dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(GRBM_SOFT_RESET, tmp);

		tmp = RREG32(GRBM_SOFT_RESET);



		udelay(50);



		tmp &= ~grbm_soft_reset;

		WREG32(GRBM_SOFT_RESET, tmp);

		tmp = RREG32(GRBM_SOFT_RESET);

	}



	if (srbm_soft_reset) {

		tmp = RREG32(SRBM_SOFT_RESET);

		tmp |= srbm_soft_reset;

		dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(SRBM_SOFT_RESET, tmp);

		tmp = RREG32(SRBM_SOFT_RESET);



		udelay(50);



		tmp &= ~srbm_soft_reset;

		WREG32(SRBM_SOFT_RESET, tmp);

		tmp = RREG32(SRBM_SOFT_RESET);

	}



	/* Wait a little for things to settle down */

	udelay(50);



	evergreen_mc_resume(rdev, &save);

	udelay(50);



#if 0

	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {

		if (RREG32(GRBM_STATUS) & GUI_ACTIVE)

			ret = -EAGAIN;

	}



	if (reset_mask & RADEON_RESET_DMA) {

		if (!(RREG32(DMA_STATUS_REG) & DMA_IDLE))

			ret = -EAGAIN;

	}

#endif



	if (!ret)

		r600_set_bios_scratch_engine_hung(rdev, false);



	evergreen_print_gpu_status_regs(rdev);



	return 0;

}
@@ -2460,7 +2468,8 @@ int evergreen_asic_reset(struct radeon_device *rdev) 
{

	return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

					       RADEON_RESET_COMPUTE |

					       RADEON_RESET_DMA));

					       RADEON_RESET_DMA |

						RADEON_RESET_CP));

}



/* Interrupts */