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Commit d3cb781e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: rework GPU reset on r6xx/r7xx 



Update the code to better match the recommended
programming sequence for soft reset.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 410a3418

drivers/gpu/drm/radeon/r600.c

+127 −122
Original line number Diff line number Diff line
@@ -1266,33 +1266,8 @@ void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 
	WREG32(R600_BIOS_3_SCRATCH, tmp);

}



/* We doesn't check that the GPU really needs a reset we simply do the

 * reset, it's up to the caller to determine if the GPU needs one. We

 * might add an helper function to check that.

 */

static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)

static void r600_print_gpu_status_regs(struct radeon_device *rdev)

{

	u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |

				S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |

				S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |

				S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |

				S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |

				S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |

				S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |

				S_008010_GUI_ACTIVE(1);

	u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |

			S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |

			S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |

			S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |

			S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |

			S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |

			S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |

			S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);

	u32 tmp;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		return;



	dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",

		 RREG32(R_008010_GRBM_STATUS));

	dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
@@ -1307,14 +1282,70 @@ static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev) 
		 RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		 RREG32(CP_STAT));

	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));

}



static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

	struct rv515_mc_save save;

	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

	u32 tmp;

	int ret = 0;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP);



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		reset_mask &= ~RADEON_RESET_DMA;



	if (reset_mask == 0)

		return 0;



	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);



	r600_print_gpu_status_regs(rdev);



	r600_set_bios_scratch_engine_hung(rdev, true);



	rv515_mc_stop(rdev, &save);

	if (r600_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	/* Disable CP parsing/prefetching */

	if (rdev->family >= CHIP_RV770)

		WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));

	else

		WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));



	/* Check if any of the rendering block is busy and reset it */

	if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||

	    (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {

		tmp = S_008020_SOFT_RESET_CR(1) |

	/* disable the RLC */

	WREG32(RLC_CNTL, 0);



	if (reset_mask & RADEON_RESET_DMA) {

		/* Disable DMA */

		tmp = RREG32(DMA_RB_CNTL);

		tmp &= ~DMA_RB_ENABLE;

		WREG32(DMA_RB_CNTL, tmp);

	}



	mdelay(50);



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {

		if (rdev->family >= CHIP_RV770)

			grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |

				S_008020_SOFT_RESET_CB(1) |

				S_008020_SOFT_RESET_PA(1) |

				S_008020_SOFT_RESET_SC(1) |

				S_008020_SOFT_RESET_SPI(1) |

				S_008020_SOFT_RESET_SX(1) |

				S_008020_SOFT_RESET_SH(1) |

				S_008020_SOFT_RESET_TC(1) |

				S_008020_SOFT_RESET_TA(1) |

				S_008020_SOFT_RESET_VC(1) |

				S_008020_SOFT_RESET_VGT(1);

		else

			grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |

				S_008020_SOFT_RESET_DB(1) |

				S_008020_SOFT_RESET_CB(1) |

				S_008020_SOFT_RESET_PA(1) |
@@ -1327,101 +1358,82 @@ static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev) 
				S_008020_SOFT_RESET_TA(1) |

				S_008020_SOFT_RESET_VC(1) |

				S_008020_SOFT_RESET_VGT(1);

		dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(R_008020_GRBM_SOFT_RESET, tmp);

		RREG32(R_008020_GRBM_SOFT_RESET);

		mdelay(15);

		WREG32(R_008020_GRBM_SOFT_RESET, 0);

	}

	/* Reset CP (we always reset CP) */

	tmp = S_008020_SOFT_RESET_CP(1);

	dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);

	WREG32(R_008020_GRBM_SOFT_RESET, tmp);

	RREG32(R_008020_GRBM_SOFT_RESET);

	mdelay(15);

	WREG32(R_008020_GRBM_SOFT_RESET, 0);



	dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",

		RREG32(R_008010_GRBM_STATUS));

	dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",

		RREG32(R_008014_GRBM_STATUS2));

	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",

		RREG32(R_000E50_SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	if (reset_mask & RADEON_RESET_CP) {

		grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |

			S_008020_SOFT_RESET_VGT(1);



		srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);

	}



static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)

{

	u32 tmp;



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		return;



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));



	/* Disable DMA */

	tmp = RREG32(DMA_RB_CNTL);

	tmp &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL, tmp);



	/* Reset dma */

	if (reset_mask & RADEON_RESET_DMA) {

		if (rdev->family >= CHIP_RV770)

		WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);

			srbm_soft_reset |= RV770_SOFT_RESET_DMA;

		else

		WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));

			srbm_soft_reset |= SOFT_RESET_DMA;

	}



static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

	struct rv515_mc_save save;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);

	if (grbm_soft_reset) {

		tmp = RREG32(R_008020_GRBM_SOFT_RESET);

		tmp |= grbm_soft_reset;

		dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(R_008020_GRBM_SOFT_RESET, tmp);

		tmp = RREG32(R_008020_GRBM_SOFT_RESET);



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		reset_mask &= ~RADEON_RESET_DMA;

		udelay(50);



	if (reset_mask == 0)

		return 0;

		tmp &= ~grbm_soft_reset;

		WREG32(R_008020_GRBM_SOFT_RESET, tmp);

		tmp = RREG32(R_008020_GRBM_SOFT_RESET);

	}



	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

	if (srbm_soft_reset) {

		tmp = RREG32(SRBM_SOFT_RESET);

		tmp |= srbm_soft_reset;

		dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(SRBM_SOFT_RESET, tmp);

		tmp = RREG32(SRBM_SOFT_RESET);



	r600_set_bios_scratch_engine_hung(rdev, true);

		udelay(50);



	rv515_mc_stop(rdev, &save);

	if (r600_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

		tmp &= ~srbm_soft_reset;

		WREG32(SRBM_SOFT_RESET, tmp);

		tmp = RREG32(SRBM_SOFT_RESET);

	}



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))

		r600_gpu_soft_reset_gfx(rdev);



	if (reset_mask & RADEON_RESET_DMA)

		r600_gpu_soft_reset_dma(rdev);



	/* Wait a little for things to settle down */

	mdelay(1);



	rv515_mc_resume(rdev, &save);

	udelay(50);



#if 0

	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {

		if (RREG32(GRBM_STATUS) & GUI_ACTIVE)

			ret = -EAGAIN;

	}



	if (reset_mask & RADEON_RESET_DMA) {

		if (!(RREG32(DMA_STATUS_REG) & DMA_IDLE))

			ret = -EAGAIN;

	}

#endif



	if (!ret)

		r600_set_bios_scratch_engine_hung(rdev, false);



	return 0;

	r600_print_gpu_status_regs(rdev);



	return ret;

}



int r600_asic_reset(struct radeon_device *rdev)

{

	return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

					  RADEON_RESET_COMPUTE |

					  RADEON_RESET_DMA |

					  RADEON_RESET_CP));

}



bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
@@ -1465,13 +1477,6 @@ bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 
	return radeon_ring_test_lockup(rdev, ring);

}



int r600_asic_reset(struct radeon_device *rdev)

{

	return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

					  RADEON_RESET_COMPUTE |

					  RADEON_RESET_DMA));

}



u32 r6xx_remap_render_backend(struct radeon_device *rdev,

			      u32 tiling_pipe_num,

			      u32 max_rb_num,

drivers/gpu/drm/radeon/r600d.h

+2 −0
Original line number Diff line number Diff line
@@ -182,6 +182,8 @@ 
#define	CP_COHER_BASE					0x85F8

#define	CP_DEBUG					0xC1FC

#define	R_0086D8_CP_ME_CNTL			0x86D8

#define		S_0086D8_CP_PFP_HALT(x)			(((x) & 1)<<26)

#define		C_0086D8_CP_PFP_HALT(x)			((x) & 0xFBFFFFFF)

#define		S_0086D8_CP_ME_HALT(x)			(((x) & 1)<<28)

#define		C_0086D8_CP_ME_HALT(x)			((x) & 0xEFFFFFFF)

#define	CP_ME_RAM_DATA					0xC160