Merge "ARM: dts: msm: Update the clock_gpucc node on SM6150" (b522f495) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/devicetree/bindings/clock/qcom,gcc.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -23,6 +23,7 @@ Required properties :
		"qcom,gcc-sdmshrike"
		"qcom,gcc-qcs405"
		"qcom,gcc-mdss-qcs405"
		"qcom,gcc-sm6150"

		- reg : shall contain base register location and length
		- #clock-cells : shall contain 1

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

+6 −5

Original line number	Diff line number	Diff line
		@@ -4,21 +4,22 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
		Required properties :
		- compatible : shall contain one of the following:
		"qcom,gpucc-sm8150",
		"qcom,gpucc-sdmshrike".
		"qcom,gpucc-sdmshrike",
		"qcom,gpucc-sm6150".

		- reg : shall contain base register offset and size.
		- reg-names: names of registers listed in the same order as in the reg property.
		Must contain "cc_base".
		- #clock-cells : shall contain 1.
		- #reset-cells : shall contain 1.
		- #clock-cells : from common clock binding, shall contain 1.
		- #reset-cells : from common reset binding, shall contain 1.
		- vdd_cx-supply : The vdd_cx logic rail supply.
		- vdd_mx-supply : The vdd_mx logic rail supply.

		Optional properties :
		- #power-domain-cells : shall contain 1.
		- #power-domain-cells : from generic power domain binding, shall contain 1.

		Example:
		clock_gpucc: qcom,gpucc {
		clock_gpucc: clock-controller@0x2c90000 {
		compatible = "qcom,gpucc-sm8150";
		reg = <0x2c90000 0x9000>;
		reg-names = "cc_base";

arch/arm64/boot/dts/qcom/sm6150-gdsc.dtsi

+14 −32

Original line number	Diff line number	Diff line
		@@ -14,7 +14,7 @@
		&soc {
		/* GDSCs in Global CC */
		emac_gdsc: qcom,gdsc@106004 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "emac_gdsc";
		reg = <0x106004 0x4>;
		qcom,poll-cfg-gdscr;
		@@ -22,7 +22,7 @@
		};

		pcie_0_gdsc: qcom,gdsc@16b004 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "pcie_0_gdsc";
		reg = <0x16b004 0x4>;
		qcom,poll-cfg-gdscr;
		@@ -30,7 +30,7 @@
		};

		ufs_phy_gdsc: qcom,gdsc@177004 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "ufs_phy_gdsc";
		reg = <0x177004 0x4>;
		qcom,poll-cfg-gdscr;
		@@ -38,7 +38,7 @@
		};

		usb20_sec_gdsc: qcom,gdsc@1a6004 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "usb20_sec_gdsc";
		reg = <0x1a6004 0x4>;
		qcom,poll-cfg-gdscr;
		@@ -46,7 +46,7 @@
		};

		usb30_prim_gdsc: qcom,gdsc@10f004 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "usb30_prim_gdsc";
		reg = <0x10f004 0x4>;
		qcom,poll-cfg-gdscr;
		@@ -54,7 +54,7 @@
		};

		hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
		reg = <0x17d040 0x4>;
		qcom,no-status-check-on-disable;
		@@ -63,7 +63,7 @@
		};

		hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
		reg = <0x17d044 0x4>;
		qcom,no-status-check-on-disable;
		@@ -72,7 +72,7 @@
		};

		hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
		reg = <0x17d048 0x4>;
		qcom,no-status-check-on-disable;
		@@ -81,7 +81,7 @@
		};

		hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
		reg = <0x17d04c 0x4>;
		qcom,no-status-check-on-disable;
		@@ -90,7 +90,7 @@
		};

		hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
		reg = <0x17d050 0x4>;
		qcom,no-status-check-on-disable;
		@@ -99,7 +99,7 @@
		};

		hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
		reg = <0x17d054 0x4>;
		qcom,no-status-check-on-disable;
		@@ -108,7 +108,7 @@
		};

		hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
		reg = <0x17d058 0x4>;
		qcom,no-status-check-on-disable;
		@@ -116,24 +116,6 @@
		status = "disabled";
		};

		hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
		reg = <0x17d05c 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
		reg = <0x17d060 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		/* GDSCs in Camera CC */
		bps_gdsc: qcom,gdsc@ad06004 {
		compatible = "regulator-fixed";
		@@ -194,7 +176,7 @@
		};

		gpu_cx_gdsc: qcom,gdsc@509106c {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "gpu_cx_gdsc";
		reg = <0x509106c 0x4>;
		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
		@@ -205,7 +187,7 @@
		};

		gpu_gx_gdsc: qcom,gdsc@509100c {
		compatible = "regulator-fixed";
		compatible = "qcom,gdsc";
		regulator-name = "gpu_gx_gdsc";
		reg = <0x509100c 0x4>;
		qcom,poll-cfg-gdscr;

arch/arm64/boot/dts/qcom/sm6150.dtsi

+14 −12

Original line number	Diff line number	Diff line
		@@ -610,8 +610,11 @@
		};

		clock_gcc: qcom,gcc {
		compatible = "qcom,dummycc";
		clock-output-names = "gcc_clocks";
		compatible = "qcom,gcc-sm6150", "syscon";
		reg = <0x100000 0x1f0000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&pm6150_s1_level>;
		vdd_cx_ao-supply = <&pm6150_s1_level_ao>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		};
		@@ -638,8 +641,11 @@
		};

		clock_gpucc: qcom,gpupcc {
		compatible = "qcom,dummycc";
		clock-output-names = "gpucc_clocks";
		compatible = "qcom,gpucc-sm6150", "syscon";
		reg = <0x5090000 0x9000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&pm6150_s1_level>;
		vdd_mx-supply = <&pm6150_s3_level>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		};
		@@ -1625,14 +1631,6 @@
		status = "ok";
		};

		&hlos1_vote_turing_mmu_tbu0_gdsc {
		status = "ok";
		};

		&hlos1_vote_turing_mmu_tbu1_gdsc {
		status = "ok";
		};

		&bps_gdsc {
		status = "ok";
		};
		@@ -1662,6 +1660,10 @@
		};

		&gpu_gx_gdsc {
		clock-names = "core_root_clk";
		clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK_SRC>;
		qcom,force-enable-root-clk;
		parent-supply = <&pm6150_s1_level>;
		status = "ok";
		};

drivers/clk/qcom/Kconfig

+17 −0

Original line number	Diff line number	Diff line
		@@ -341,3 +341,20 @@ config CLOCK_CPU_QCS405
		based devices.
		Say Y if you want to support CPU clock scaling using
		CPUfreq drivers for dynamic power management.

		config MSM_GCC_SM6150
		tristate "SM6150 Global Clock Controller"
		depends on COMMON_CLK_QCOM
		help
		Support for the global clock controller on Qualcomm Technologies, Inc
		SM6150 devices.
		Say Y if you want to use peripheral devices such as UART, SPI, I2C,
		USB, UFS, SD/eMMC, PCIe, etc.

		config MSM_GPUCC_SM6150
		tristate "SM6150 graphics Clock Controller"
		depends on COMMON_CLK_QCOM
		help
		Support for the graphics clock controller on Qualcomm Technologies, Inc.
		SM6150 devices.
		Say Y if you want to support graphics clocks.