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Commit 0a75c848 authored by Amit Nischal's avatar Amit Nischal Committed by Odelu Kukatla
Browse files

ARM: dts: msm: Update the clock_gpucc node on SM6150 



Update the GPUCC clock controller device node to register to
actual GPUCC driver. Also update the GPUCC GDSCs by replacing
the dummy nodes with actual GDSC regulator driver.

Change-Id: If6bfe9e088060f4a4f9c5e0d4241d8f4bfcea89c
Signed-off-by: default avatarAmit Nischal <anischal@codeaurora.org>
parent 1acf1a1a

arch/arm64/boot/dts/qcom/sm6150-gdsc.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -176,7 +176,7 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@509106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_cx_gdsc";

		reg = <0x509106c 0x4>;

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -187,7 +187,7 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@509100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_gx_gdsc";

		reg = <0x509100c 0x4>;

		qcom,poll-cfg-gdscr;

arch/arm64/boot/dts/qcom/sm6150.dtsi

+9 −2
Original line number Diff line number Diff line
@@ -640,8 +640,11 @@ 
	};



	clock_gpucc: qcom,gpupcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		compatible = "qcom,gpucc-sm6150", "syscon";

		reg = <0x5090000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm6150_s1_level>;

		vdd_mx-supply = <&pm6150_s3_level>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1609,6 +1612,10 @@ 
};



&gpu_gx_gdsc {

	clock-names = "core_root_clk";

	clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK_SRC>;

	qcom,force-enable-root-clk;

	parent-supply = <&pm6150_s1_level>;

	status = "ok";

};