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Commit ac49d25a authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: Enable GPUCC and NPUCC drivers for SDMSTEPPE"

parents a5379aff c2018928

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

+2 −1
Original line number Diff line number Diff line
@@ -5,7 +5,8 @@ Required properties : 
- compatible : shall contain one of the following:

		"qcom,gpucc-sm8150",

		"qcom,gpucc-sdmshrike",

		"qcom,gpucc-sm6150".

		"qcom,gpucc-sm6150",

		"qcom,gpucc-sdmmagpie".



- reg : shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.

arch/arm64/boot/dts/qcom/sdmmagpie-gdsc.dtsi

+14 −2
Original line number Diff line number Diff line
@@ -175,8 +175,18 @@ 
		reg = <0x5091540 0x4>;

	};



	gpu_gx_domain_addr: syscon@0x5091508 {

		compatible = "syscon";

		reg = <0x5091508 0x4>;

	};



	gpu_gx_sw_reset: syscon@0x5091008 {

		compatible = "syscon";

		reg = <0x5091008 0x4>;

	};



	gpu_cx_gdsc: qcom,gdsc@509106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_cx_gdsc";

		reg = <0x509106c 0x4>;

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -187,10 +197,12 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@509100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_gx_gdsc";

		reg = <0x509100c 0x4>;

		qcom,poll-cfg-gdscr;

		domain-addr = <&gpu_gx_domain_addr>;

		sw-reset = <&gpu_gx_sw_reset>;

		status = "disabled";

	};

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+12 −2
Original line number Diff line number Diff line
@@ -661,8 +661,12 @@ 
	};



	clock_gpucc: qcom,gpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		compatible = "qcom,gpucc-sdmmagpie", "syscon";

		reg = <0x5090000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_gfx-supply = <&VDD_GFX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1780,10 +1784,16 @@ 
};



&gpu_cx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&gpu_gx_gdsc {

	clock-names = "core_root_clk";

	clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK_SRC>;

	qcom,force-enable-root-clk;

	parent-supply = <&VDD_GFX_LEVEL>;

	qcom,reset-aon-logic;

	status = "ok";

};

arch/arm64/configs/vendor/sdmsteppe-perf_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -492,6 +492,8 @@ CONFIG_MSM_CAMCC_SM6150=y 
CONFIG_MSM_DISPCC_SM6150=y

CONFIG_MSM_GCC_SDMMAGPIE=y

CONFIG_MSM_VIDEOCC_SDMMAGPIE=y

CONFIG_MSM_NPUCC_SDMMAGPIE=y

CONFIG_MSM_GPUCC_SDMMAGPIE=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y

arch/arm64/configs/vendor/sdmsteppe_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -509,6 +509,8 @@ CONFIG_MSM_CAMCC_SM6150=y 
CONFIG_MSM_DISPCC_SM6150=y

CONFIG_MSM_GCC_SDMMAGPIE=y

CONFIG_MSM_VIDEOCC_SDMMAGPIE=y

CONFIG_MSM_NPUCC_SDMMAGPIE=y

CONFIG_MSM_GPUCC_SDMMAGPIE=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y