Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ac0f6f92 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm 

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (100 commits)
  ARM: Eliminate decompressor -Dstatic= PIC hack
  ARM: 5958/1: ARM: U300: fix inverted clk round rate
  ARM: 5956/1: misplaced parentheses
  ARM: 5955/1: ep93xx: move timer defines into core.c and document
  ARM: 5954/1: ep93xx: move gpio interrupt support to gpio.c
  ARM: 5953/1: ep93xx: fix broken build of clock.c
  ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig
  ARM: 5949/1: NUC900 add gpio virtual memory map
  ARM: 5948/1: Enable timer0 to time4 clock support for nuc910
  ARM: 5940/2: ARM: MMCI: remove custom DBG macro and printk
  ARM: make_coherent(): fix problems with highpte, part 2
  MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
  ARM: 5945/1: ep93xx: include correct irq.h in core.c
  ARM: 5933/1: amba-pl011: support hardware flow control
  ARM: 5930/1: Add PKMAP area description to memory.txt.
  ARM: 5929/1: Add checks to detect overlap of memory regions.
  ARM: 5928/1: Change type of VMALLOC_END to unsigned long.
  ARM: 5927/1: Make delimiters of DMA area globally visibly.
  ARM: 5926/1: Add "Virtual kernel memory..." printout.
  ARM: 5920/1: OMAP4: Enable L2 Cache
  ...

Fix up trivial conflict in arch/arm/mach-mx25/clock.c
parents b1bf9368 9f33be2c

Documentation/arm/memory.txt

+5 −1
Original line number Diff line number Diff line
@@ -59,7 +59,11 @@ PAGE_OFFSET high_memory-1 Kernel direct-mapped RAM region. 
				This maps the platforms RAM, and typically

				maps all platform RAM in a 1:1 relationship.



TASK_SIZE	PAGE_OFFSET-1	Kernel module space

PKMAP_BASE	PAGE_OFFSET-1	Permanent kernel mappings

				One way of mapping HIGHMEM pages into kernel

				space.



MODULES_VADDR	MODULES_END-1	Kernel module space

				Kernel modules inserted via insmod are

				placed here using dynamic mappings.

Documentation/cachetlb.txt

+3 −3
Original line number Diff line number Diff line
@@ -88,12 +88,12 @@ changes occur: 
	This is used primarily during fault processing.



5) void update_mmu_cache(struct vm_area_struct *vma,

			 unsigned long address, pte_t pte)

			 unsigned long address, pte_t *ptep)



	At the end of every page fault, this routine is invoked to

	tell the architecture specific code that a translation

	described by "pte" now exists at virtual address "address"

	for address space "vma->vm_mm", in the software page tables.

	now exists at virtual address "address" for address space

	"vma->vm_mm", in the software page tables.



	A port may use this information in any way it so chooses.

	For example, it could use this event to pre-load TLB

arch/alpha/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -329,7 +329,7 @@ extern pgd_t swapper_pg_dir[1024]; 
 * tables contain all the necessary information.

 */

extern inline void update_mmu_cache(struct vm_area_struct * vma,

	unsigned long address, pte_t pte)

	unsigned long address, pte_t *ptep)

{

}

arch/arm/Kconfig

+51 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ config ARM 
	select HAVE_IDE

	select RTC_LIB

	select SYS_SUPPORTS_APM_EMULATION

	select GENERIC_ATOMIC64 if (!CPU_32v6K)

	select HAVE_OPROFILE

	select HAVE_ARCH_KGDB

	select HAVE_KPROBES if (!XIP_KERNEL)
@@ -20,6 +21,8 @@ config ARM 
	select HAVE_GENERIC_DMA_COHERENT

	select HAVE_KERNEL_GZIP

	select HAVE_KERNEL_LZO

	select HAVE_PERF_EVENTS

	select PERF_USE_VMALLOC

	help

	  The ARM series is a line of low-power-consumption RISC chip designs

	  licensed by ARM Ltd and targeted at embedded applications and
@@ -52,6 +55,9 @@ config HAVE_TCM 
	bool

	select GENERIC_ALLOCATOR



config HAVE_PROC_CPU

	bool



config NO_IOPORT

	bool
@@ -161,6 +167,11 @@ config ARCH_MTD_XIP 
config GENERIC_HARDIRQS_NO__DO_IRQ

	def_bool y



config ARM_L1_CACHE_SHIFT_6

	bool

	help

	  Setting ARM L1 cache line size to 64 Bytes.



if OPROFILE



config OPROFILE_ARMV6
@@ -550,10 +561,20 @@ config ARCH_W90X900 
	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/

		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>



config ARCH_NUC93X

	bool "Nuvoton NUC93X CPU"

	select CPU_ARM926T

	select HAVE_CLK

	select COMMON_CLKDEV

	help

	  Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a

	  low-power and high performance MPEG-4/JPEG multimedia controller chip.



config ARCH_PNX4008

	bool "Philips Nexperia PNX4008 Mobile"

	select CPU_ARM926T

	select HAVE_CLK

	select COMMON_CLKDEV

	help

	  This enables support for Philips PNX4008 mobile platform.
@@ -638,6 +659,7 @@ config ARCH_S5PC1XX 
	select GENERIC_GPIO

	select HAVE_CLK

	select CPU_V7

	select ARM_L1_CACHE_SHIFT_6

	help

	  Samsung S5PC1XX series based systems
@@ -785,6 +807,8 @@ source "arch/arm/plat-nomadik/Kconfig" 


source "arch/arm/mach-ns9xxx/Kconfig"



source "arch/arm/mach-nuc93x/Kconfig"



source "arch/arm/plat-omap/Kconfig"



source "arch/arm/mach-omap1/Kconfig"
@@ -867,6 +891,11 @@ config XSCALE_PMU 
	depends on CPU_XSCALE && !XSCALE_PMU_TIMER

	default y



config CPU_HAS_PMU

	depends on CPU_V6 || CPU_V7 || XSCALE_PMU

	default y

	bool



if !MMU

source "arch/arm/Kconfig-nommu"

endif
@@ -921,6 +950,19 @@ config ARM_ERRATA_460075 
	  ACTLR register. Note that setting specific bits in the ACTLR register

	  may not be available in non-secure mode.



config PL310_ERRATA_588369

	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"

	depends on CACHE_L2X0 && ARCH_OMAP4

	help

	   The PL310 L2 cache controller implements three types of Clean &

	   Invalidate maintenance operations: by Physical Address

	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).

	   They are architecturally defined to behave as the execution of a

	   clean operation followed immediately by an invalidate operation,

	   both performing to the same memory location. This functionality

	   is not correctly implemented in PL310 as clean lines are not

	   invalidated as a result of these operations. Note that this errata

	   uses Texas Instrument's secure monitor api.

endmenu



source "arch/arm/common/Kconfig"
@@ -1171,6 +1213,14 @@ config HIGHPTE 
	depends on HIGHMEM

	depends on !OUTER_CACHE



config HW_PERF_EVENTS

	bool "Enable hardware performance counter support for perf events"

	depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)

	default y

	help

	  Enable hardware performance counter support for perf events. If

	  disabled, perf events will use software events only.



source "mm/Kconfig"



config LEDS
@@ -1230,6 +1280,7 @@ config ALIGNMENT_TRAP 
	bool

	depends on CPU_CP15_MMU

	default y if !ARCH_EBSA110

	select HAVE_PROC_CPU if PROC_FS

	help

	  ARM processors cannot fetch/store information which is not

	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ machine-$(CONFIG_ARCH_U300) := u300 
machine-$(CONFIG_ARCH_U8500)		:= ux500

machine-$(CONFIG_ARCH_VERSATILE)	:= versatile

machine-$(CONFIG_ARCH_W90X900)		:= w90x900

machine-$(CONFIG_ARCH_NUC93X)		:= nuc93x

machine-$(CONFIG_FOOTBRIDGE)		:= footbridge



# Platform directory name.  This list is sorted alphanumerically