Merge branches 'clks' and 'pnx' into devel

VERSION = 2

PATCHLEVEL = 6

SUBLEVEL = 33

EXTRAVERSION = -rc4

EXTRAVERSION = -rc5

NAME = Man-Eating Seals of Antiquity

# *DOCUMENTATION*

	bool "Philips Nexperia PNX4008 Mobile"

	select CPU_ARM926T

	select HAVE_CLK

	select COMMON_CLKDEV

	help

	  This enables support for Philips PNX4008 mobile platform.

}

EXPORT_SYMBOL(clkdev_add);

void __init clkdev_add_table(struct clk_lookup *cl, size_t num)

{

	mutex_lock(&clocks_mutex);

	while (num--) {

		list_add_tail(&cl->node, &clocks);

		cl++;

	}

	mutex_unlock(&clocks_mutex);

}

#define MAX_DEV_ID	20

#define MAX_CON_ID	16

 *	Please note that the implementation of these, and the required

 *	effects are cache-type (VIVT/VIPT/PIPT) specific.

 *

 *	flush_cache_kern_all()

 *	flush_kern_all()

 *

 *		Unconditionally clean and invalidate the entire cache.

 *

 *	flush_cache_user_mm(mm)

 *	flush_user_all()

 *

 *		Clean and invalidate all user space cache entries

 *		before a change of page tables.

 *

 *	flush_cache_user_range(start, end, flags)

 *	flush_user_range(start, end, flags)

 *

 *		Clean and invalidate a range of cache entries in the

 *		specified address space before a change of page tables.

 *		- start  - virtual start address

 *		- end    - virtual end address

 *

 *	coherent_user_range(start, end)

 *

 *		Ensure coherency between the Icache and the Dcache in the

 *		region described by start, end.  If you have non-snooping

 *		Harvard caches, you need to implement this function.

 *		- start  - virtual start address

 *		- end    - virtual end address

 *

 *	flush_kern_dcache_area(kaddr, size)

 *

 *		Ensure that the data held in page is written back.

 *		- kaddr  - page address

 *		- size   - region size

 *

 *	DMA Cache Coherency

 *	===================

 *

void clkdev_add(struct clk_lookup *cl);

void clkdev_drop(struct clk_lookup *cl);

void clkdev_add_table(struct clk_lookup *, size_t);

int clk_add_alias(const char *, const char *, char *, struct device *);

#endif