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Commit a7550ff2 authored by Xiaowen Wu's avatar Xiaowen Wu
Browse files

drm/msm/shd: fix plane stage check in shared display 



Fix plane stage setting in shared display and change debug level for stage
validation. Shared display has less stages than normal display and might
fail stage validation. Change debug level for stage validation to avoid
error messages flooding the console.

Change-Id: I226aafcf124af2212bdafcb02f87c99538b956cf
Signed-off-by: default avatarXiaowen Wu <wxiaowen@codeaurora.org>
parent 3638c290

drivers/gpu/drm/msm/shd/shd_drm.c

+4 −3
Original line number Diff line number Diff line
@@ -405,8 +405,9 @@ static int shd_crtc_validate_shared_display(struct drm_crtc *crtc, 
	/* check z-pos for all planes */

	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {

		sde_pstate = to_sde_plane_state(pstate);

		if (sde_pstate->stage >= shd_crtc->display->stage_range.size) {

			SDE_ERROR("plane stage %d is larger than maximum %d\n",

		if (sde_pstate->stage >=

			shd_crtc->display->stage_range.size + SDE_STAGE_0) {

			SDE_DEBUG("plane stage %d is larger than maximum %d\n",

				sde_pstate->stage,

				shd_crtc->display->stage_range.size);

			return -EINVAL;
@@ -417,7 +418,7 @@ static int shd_crtc_validate_shared_display(struct drm_crtc *crtc, 
	for (i = 0; i < sde_crtc_state->num_dim_layers; i++) {

		if (sde_crtc_state->dim_layer[i].stage >=

			shd_crtc->display->stage_range.size + SDE_STAGE_0) {

			SDE_ERROR("dim stage %d is larger than maximum %d\n",

			SDE_DEBUG("dim stage %d is larger than maximum %d\n",

				sde_crtc_state->dim_layer[i].stage,

				shd_crtc->display->stage_range.size);

			return -EINVAL;

drivers/gpu/drm/msm/shd/shd_hw.c

+2 −10
Original line number Diff line number Diff line
@@ -188,9 +188,7 @@ static void _sde_shd_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx, 
{

	struct sde_shd_hw_ctl *hw_ctl;

	int i, j;

	int stages;

	int pipes_per_stage;

	int stage_offset = 0;

	u32 pipe_idx, rect_idx;

	const struct ctl_sspp_stage_reg_map *sspp_cfg;

	u32 mixercfg[CTL_NUM_EXT] = {CTL_MIXER_BORDER_OUT, 0, 0, 0};
@@ -202,10 +200,6 @@ static void _sde_shd_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx, 


	hw_ctl = container_of(ctx, struct sde_shd_hw_ctl, base);



	stages = hw_ctl->range.size - 1;

	if (stages < 0)

		return;



	if (test_bit(SDE_MIXER_SOURCESPLIT,

		&ctx->mixer_hw_caps->features))

		pipes_per_stage = PIPES_PER_STAGE;
@@ -217,9 +211,7 @@ static void _sde_shd_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx, 
	if (!stage_cfg)

		goto exit;



	stage_offset = hw_ctl->range.start;



	for (i = 0; i <= stages; i++) {

	for (i = SDE_STAGE_0; i <= hw_ctl->range.size; i++) {

		for (j = 0 ; j < pipes_per_stage; j++) {

			pipe_idx = stage_cfg->stage[i][j];

			if (!pipe_idx || pipe_idx >= SSPP_MAX)
@@ -232,7 +224,7 @@ static void _sde_shd_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx, 
			if (!sspp_cfg->bits)

				continue;



			stage_value = i + stage_offset + 1;

			stage_value = i + hw_ctl->range.start + 1;

			mask = (1 << sspp_cfg->bits) - 1;

			value = mask & stage_value;

			mixercfg[sspp_cfg->ext] |= (value << sspp_cfg->start);