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Commit a561eb7c authored by Jack Pham's avatar Jack Pham Committed by Adam Bickett
Browse files

ARM: dts: msm: Enable primary USB device nodes on sdmshrike 



Add sdmshrike-usb.dtsi which defines the primary USB controller
and high speed PHY nodes. Also add the emulation PHY for  RUMI.

Change-Id: I3a9bb83de327ede5be9123158800374c3c550540
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent edbb2a62

arch/arm64/boot/dts/qcom/sdmshrike-rumi.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -10,6 +10,39 @@ 
 * GNU General Public License for more details.

 */



&soc {

	usb_emu_phy: usb_emu_phy@a720000 {

		compatible = "qcom,usb-emu-phy";

		reg = <0x0a720000 0x9500>,

		      <0x0a6f8800 0x100>;

		reg-names = "base", "qcratch_base";



		qcom,emu-init-seq = <0xfff0 0x4

				     0xfff3 0x4

				     0x40 0x4

				     0xfff3 0x4

				     0xfff0 0x4

				     0x100000 0x20

				     0x0 0x20

				     0x1a0 0x20

				     0x100000 0x3c

				     0x0 0x3c

				     0x10060 0x3c

				     0x0 0x4>;

	};

};



&usb0 {

	dwc3@a600000 {

		usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;

		maximum-speed = "high-speed";

	};

};



&usb2_phy0 {

	status = "disabled";

};



&sdhc_2 {

	vdd-supply = <&pm855_2_l17>;

	qcom,vdd-voltage-level = <2960000 2960000>;

arch/arm64/boot/dts/qcom/sdmshrike-usb.dtsi

0 → 100644
+132 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/phy/qcom,sdm855-qmp-usb3.h>



&soc {

	/* Primary USB port related controller */

	usb0: ssusb@a600000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x0a600000 0x100000>;

		reg-names = "core_base";



		iommus = <&apps_smmu 0x140 0x0>;

		qcom,smmu-s1-bypass;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>;

		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",

				"ss_phy_irq", "dm_hs_phy_irq";

		qcom,use-pdc-interrupts;



		USB3_GDSC-supply = <&usb30_prim_gdsc>;

		clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,

			<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

			<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

					"utmi_clk", "sleep_clk", "xo";



		resets = <&clock_gcc GCC_USB30_PRIM_BCR>;

		reset-names = "core_reset";



		qcom,core-clk-rate = <200000000>;

		qcom,core-clk-rate-hs = <66666667>;

		qcom,num-gsi-evt-buffs = <0x3>;

		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;



		qcom,msm-bus,name = "usb0";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <3>;

		qcom,msm-bus,vectors-KBps =

			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,

			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,

			<MSM_BUS_MASTER_USB3

				MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,

			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>;



		dwc3@a600000 {

			compatible = "snps,dwc3";

			reg = <0x0a600000 0xcd00>;

			interrupts = <0 133 0>;

			usb-phy = <&usb2_phy0>, <&usb_nop_phy>;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,has-lpm-erratum;

			snps,hird-threshold = /bits/ 8 <0x10>;

			snps,usb3_lpm_capable;

			usb-core-id = <0>;

			tx-fifo-resize;

			maximum-speed = "high-speed";

			dr_mode = "otg";

		};



		qcom,usbbam@a704000 {

			compatible = "qcom,usb-bam-msm";

			reg = <0xa704000 0x17000>;

			interrupts = <0 132 0>;



			qcom,usb-bam-fifo-baseaddr = <0x146bb000>;

			qcom,usb-bam-num-pipes = <4>;

			qcom,disable-clk-gating;

			qcom,usb-bam-override-threshold = <0x4001>;

			qcom,usb-bam-max-mbps-highspeed = <400>;

			qcom,usb-bam-max-mbps-superspeed = <3600>;

			qcom,reset-bam-on-connect;



			qcom,pipe0 {

				label = "ssusb-qdss-in-0";

				qcom,usb-bam-mem-type = <2>;

				qcom,dir = <1>;

				qcom,pipe-num = <0>;

				qcom,peer-bam = <0>;

				qcom,peer-bam-physical-address = <0x6064000>;

				qcom,src-bam-pipe-index = <0>;

				qcom,dst-bam-pipe-index = <0>;

				qcom,data-fifo-offset = <0x0>;

				qcom,data-fifo-size = <0x1800>;

				qcom,descriptor-fifo-offset = <0x1800>;

				qcom,descriptor-fifo-size = <0x800>;

			};

		};

	};



	/* Primary USB port related High Speed PHY */

	usb2_phy0: hsphy@88e2000 {

		compatible = "qcom,usb-hsphy-snps-femto";

		reg = <0x88e2000 0x110>;

		reg-names = "hsusb_phy_base";



		vdd-supply = <&pm855_2_l5>;

		vdda18-supply = <&pm855_1_l12>;

		vdda33-supply = <&pm855_2_l16>;

		qcom,vdd-voltage-level = <0 880000 880000>;



		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "ref_clk_src";



		resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;

		reset-names = "phy_reset";

		qcom,param-override-seq = <0x43 0x70>;

	};



	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};

};

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -837,3 +837,4 @@ 
#include "sdmshrike-ion.dtsi"

#include "sdmshrike-bus.dtsi"

#include "msm-arm-smmu-sdmshrike.dtsi"

#include "sdmshrike-usb.dtsi"